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CXD2721Q-1
Single-Chip Digital Signal Processor for Karaoke
Description The CXD2721Q-1 is a Karaoke LSI suitable for use in video CD/LD/CD-G/CD and the like. A large capacity DRAM and AD/DA converters are built in, and a Karaoke mode providing simple surround and Karaoke functions such as key control, microphone echo and voice cancelling, and a music mode providing functions such as surround, parametric equalizer and bass/treble tone control are contained on a single chip. Features * 3-channel 1-bit AD converter, decimation filter and prefilter operational amplifier S/N ratio: 92dB THD + N: 0.02% Filter pass band ripple: 0.5dB or less Filter stop band attenuation: -41dB or less (all characteristics are typical values) * 2-channel 1-bit DA converter, oversampling filter and post filter S/N ratio: 97dB THD + N: 0.005% Filter pass band ripple: 0.2dB or less Filter stop band attenuation: -41dB or less (all characteristics are typical values) * In addition to analog I/O, digital I/O (2-channel input/2-channel output) are provided. The interface also supports a wide variety of formats. * 128K-bit DRAM for key control, microphone echo and surround processing Functions * Key controller pitch settings can be varied to a maximum of 1 octave with a precision of 14 bits. * Microphone echo delay time can be varied to a maximum of 278ms (when Fs = 44.1kHz). * Voice canceller supports settings other than center using panpot volumes. * Voice parametric equalizer * Voice pitch shifter * Mixing function to support sound multiplexing software 100 pin QFP (Plastic)
* Digital de-emphasis function * Simple surround function * Music mode (switches with Karaoke mode) Compressor function Parametric equalizer function Surround function Bass/treble tone control function Structure Silicon gate CMOS Applications Equipment with Karaoke functions, such as video CD/LD/CD-G/CD, compact music centers, video games, etc. Absolute Maximum Ratings (Ta = 25C, VSS = 0V) * Supply voltage VDD VSS - 0.5 to +7.0 V * Input voltage VI VSS - 0.5 to VDD +0.5 V * Output voltage VO VSS - 0.5 to VDD +0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 4.5 to 5.25 (5.0 typ.) V * Operating temperature Ta -20 to +75 C I/O Capacitance * Input capacitance CIN 9 (max.) pF * Output capacitance COUT 11 (max.) pF * I/O capacitance CI/O 11 (max.) pF Measurement conditions: VDD = VI = 0V, F = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97110A72
CXD2721Q-1
Block Diagram
128K bit DELAY RAM DAC1 RVDT 4 MICRO COMPUTER I/F DSP
45 AOUT1 39 AO1N 40 AO1P
SCK 98 XLAT 1
29 AOUT2 DAC2 33 AO2N 34 AO2P 47 ADC1 AIN1
REDY 99 TRDT 100 LRCK 94 BCK 93 SI 92 SO 91 XMST 95
SERIAL DATA I/F
49 LO1 24 AIN2
ADC2
25 LO2 20 AIN3
CLOCK GENERATOR /TIMING CIRCUIT
ADC3
21 LO3
37
36
14
XTLI XTLO BFOT
Pin Configuration
VDD4 VDD3 VSS4 VSS3 VDD2 VSS5 NC TP TP TP TP NC
50
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TP 81 TP 82 VSS6 83 VDD5 84 TST0 85 TST1 86 TST2 87 TST3 88 VSS7 89 XS24 90 SO 91 SI 92 BCK 93 LRCK 94 XMST 95 VSS8 96 VDD6 97 SCK 98 REDY 99 TRDT 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AVD1
TP
TP
TP
TP
TP
49 LO1 48 NC
47 AIN1 46 45 AVS1 AOUT1
44 NC 43 AVS4 42 NC 41 AVD4 40 AO1P 39 AO1N 38 AVS6 37 XTLI 36 XTLO 35 AVD6
34 AO2P 33 AO2N 32 AVD5 31 NC
AOUT2
AVD0
AVD2
VDD1
VSS2
NC
RVDT
AVD3
BSL1
VSS0
BSL2
X768
LO3
XRST
BFOT
AVS0
AVS3
AVS2
NC
AIN3
NC
XWO
LO2
NC
NC
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AVS5
XLAT
VDD1
VSS1
AIN2
CXD2721Q-1
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol XLAT NC NC RVDT NC AVD0 AVS0 XRST X768 VSS0 VDD1 VSS1 XWO BFOT BSL2 BSL1 VSS2 VDD1 AVS3 AIN3 LO3 AVD3 AVD2 AIN2 LO2 AVS2 NC NC AOUT2 AVS5 NC AVD5 AO2N AO2P AVD6 -- O O -- O -- -- -- I I -- -- -- I O I I -- -- -- I O -- -- I O -- I I/O I Description Latch input for microcomputer interface. Open or fixed to Low. Open or fixed to Low. Data input for microcomputer interface. Open or fixed to Low. Digital power supply for built-in DRAM. Digital GND for built-in DRAM. System reset input. Reset when Low. Test input pin. Normally fixed to Low. Digital GND. Digital power supply. Digital GND. Normally fixed to High. Clock, frequency divider output. (384/768/256/512fs) BFOT output clock frequency division ratio setting. BFOT output clock frequency division ratio setting. Digital GND. Digital power supply. CH3 AD converter GND. CH3 AD converter analog input. (for microphone input) CH3 AD converter LPF operational amplifier inverted output. (for microphone input) CH3 AD converter power supply. CH2 AD converter power supply. CH2 AD converter analog input. CH2 AD converter LPF operational amplifier inverted output. CH2 AD converter GND. Open or fixed to Low. Open or fixed to Low. CH2 DA converter LPF output. CH2 DA converter GND. Open or fixed to Low. CH2 DA converter power supply. CH2 DA converter analog reversed phase output. (PWM) CH2 DA converter analog forward phase output. (PWM) Analog power supply for master clock.
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CXD2721Q-1
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Symbol XTLO XTLI AVS6 AO1N AO1P AVD4 NC AVS4 NC AOUT1 AVS1 AIN1 NC LO1 AVD1 NC NC VDD2 VSS3 TP TP TP TP TP TP TP TP TP TP VSS4 VDD3 TP TP TP TP
I/O O I -- O O -- Crystal oscillator circuit output. Crystal oscillator circuit input. Analog GND for master clock.
Description
CH1 DA converter analog reversed phase output. (PWM) CH1 DA converter analog forward phase output. (PWM) CH1 DA converter power supply. Open or fixed to Low.
--
CH1 DA converter GND. Open or fixed to Low.
O -- I
CH1 DA converter LPF output. CH1 AD converter GND. CH1 AD converter analog input. Open or fixed to Low.
I --
CH1 AD converter analog input. LPF operational amplifier inverted output. CH1 AD converter power supply. Open or fixed to Low. Open or fixed to Low.
-- -- O O O O O O O O O O -- -- O O O O
Digital power supply. Digital GND. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Digital GND. Digital power supply. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open.
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CXD2721Q-1
Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol TP TP TP TP TP VSS5 VDD4 TP TP TP TP TP VSS6 VDD5 TST0 TST1 TST2 TST3 VSS7 XS24 SO SI BCK LRCK XMST VSS8 VDD6 SCK REDY TRDT
I/O O O O O O -- -- O O O O O -- -- I I I I -- I O I I/O I/O I -- -- I O O
Description Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Digital GND. Digital power supply. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Test monitor pin. Normally Low output. Leave open. Digital GND. Digital power supply. Test pin. Normally fixed to Low. Test pin. Normally fixed to Low. Test pin. Normally fixed to Low. Test pin. Normally fixed to Low. Digital GND. Serial data 24-/32-bit slot selection. 24-bit slot when Low. (valid for slave mode) 1-sampling 2-channel serial data output. 1-sampling 2-channel serial data input. Serial bit transfer clock for serial I/O data SI and SO. Sampling frequency clock for serial I/O data SI and SO. BCK, LRCK master/slave mode switching input. Master mode when Low. Digital GND. Digital power supply. Shift clock input for microcomputer interface. Transfer enabling signal output for microcomputer interface. Transfer prohibited when Low. Serial data output for microcomputer interface.
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CXD2721Q-1
DC Characteristics (AVD0 to 6 = VDD0 to 6 = 4.5V to 5.25V, AVS0 to 6 = VSS0 to 8 = 0V, Ta = -20 to +75C) Item Input voltage (1) Symbol High level VIH Low level VIL Input voltage (2) Input voltage (3) High level VIH Low level VIL VIN Analog input IOH = -2.0mA IOL = 4.0mA IOH = -12.0mA IOL = 12.0mA VIH = VDD, VSS VIH = VDD, VSS VIH = VDD, VSS -10 -40 -40 250k fS = 44.1kHz 1M 125 VDD/2 VDD/2 10 40 40 2.5M 132 VSS VDD - 0.8 0.4 Schmitt input 0.8VDD 0.2VDD VDD Conditions Min. 0.7VDD 0.3VDD Typ. Max. Unit V V V V V V V V V A A A mA Applicable pins 1, 4, 5 1, 4, 5 3 3 2 6, 7, 8 6, 7, 8, 9 10 10 1, 3, 5 4 8, 9 Resistance between 5 and 10
Output voltage High level VOH (1) Low level VOL Output voltage High level VOH (2) Low level VOL Input leak current (1) Input leak current (2) Output leak current Feedback resistance Current consumption II II IOZ RFB IDD
1 XLAT, RVDT, X768, XWO, BSL2, BSL1, TST0 to TST3, XS24, SI, XMST, SCK 2 AIN1, AIN2, AIN3 3 XRST 4 During input to bidirectional pins BCK and LRCK 5 XTLI 6 During output from bidirectional pins BCK and LRCK 7 SO, BFOT 8 TRDT 9 REDY 10 XTLO
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CXD2721Q-1
AC Characteristics (AVD0 to 6 = VDD0 to 6 = 4.5V to 5.25V, AVS0 to 6 = VSS0 to 8 = 0V, Ta = -20 to +75C) Serial Audio Interface Timing [Slave mode]
BCK tSSI SI tDSSO SO tHLR LRCK tSLR
0.7VDD 0.3VDD 0.7VDD 0.3VDD
tHSI
0.7VDD 0.3VDD
[Master mode]
BCK tDLR LRCK tDMSO SO
Item SI setup time SI hold time SO delay time LRCK setup time LRCK hold time LRCK delay time SO delay time
Symbol
Conditions Slave mode Slave mode Slave mode, CL = 60pF Slave mode Slave mode Master mode, CL = 120pF Master mode, CL = 60pF
Min. 20 40
Max.
Unit ns ns
tSSI tHSI tDSSO tSLR tHLR tDLR tDMSO
50 20 40 50 100
ns ns ns ns ns
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CXD2721Q-1
Microcomputer Interface Timing [Write] * Transfer timing for address section, transfer mode section and data section LSB
RVDT Address LSB tSWL tSWH Mode MSB tDS tDH
0.7VDD 0.3VDD
Data LSB
Data MSB
SCK tSLP XLAT tLWH REDY
0.7VDD 0.3VDD
tLSD
0.7VDD 0.3VDD
tLWL
* Transfer timing from data section MSB to address section and transfer mode section
RVDT
Data MSB tSS
Address LSB
Mode MSB
0.7VDD 0.3VDD
SCK tSLD XLAT tSBD tBSP REDY tLDR
0.7VDD 0.3VDD
0.7VDD 0.3VDD
tRLP
[Read] * Transfer timing for address section and transfer mode section is the same as for write.
RVDT Mode MSB tSS SCK tSLP XLAT tLWL REDY tLDN TRDT tSDD Data LSB Data MSB tLBD
0.7VDD 0.3VDD 0.7VDD 0.3VDD
Address LSB
tRSDP
0.7VDD 0.3VDD
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CXD2721Q-1
Item RVDT setup time relative to SCK rise RVDT data hold time from SCK rise SCK Low level width SCK High level width XLAT Low level width XLAT High level width SCK rise preceding time relative to XLAT rise SCK rise wait time relative to XLAT rise Delay time to REDY fall relative to XLAT rise Delay time to REDY fall relative to SCK rise REDY fall preceding time relative to SCK rise REDY rise preceding time relative to XLAT rise REDY rise preceding time relative to SCK fall XLAT fall wait time relative to SCK rise XLAT fall delay time relative to REDY fall Delay time from XLAT rise until TRDT data becomes active Delay time from SCK rise until TRDT data becomes high-impedance Delay time from SCK fall until TRDT data is established SCK rise wait time for next transfer
Symbol
Min. 20 1t + 20 1t + 20 1t + 20 1t + 20 1t + 20 20 3t + 20
Max.
Unit ns ns ns ns ns ns ns ns
tDS tDH tSWL tSWH tLWL tLWH tSLP tLSD tLBD tSBD tBSP tRLP tRSDP tSLD tLDR tLDN tSDF tSDD tSS
3t + 50 4t + 50 20 20 20 3t + 20 20 3t + 80 3t + 80 2t + 70 2t + 40
ns ns ns ns ns ns ns ns ns ns ns
Note 1) t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs) Note 2) REDY and TRDT pins are the values for CL = 60pF.
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CXD2721Q-1
Analog Characteristics (AVD0 to 6 = VDD0 to 6 = 5.0V, AVS0 to 6 = VSS0 to 8 = 0.0V, DSP: each function = OFF, gain = 1, Ta = 25C) 1. ADC + DAC Connection Total Characteristics Total characteristics using the measurement circuit in Fig. 1, including the prefilter with built-in operational amplifier and the built-in post filter. Unless otherwise specified, the measurement conditions are as given below. * IN ....0dB (= 2.0Vrms), 1kHz * fs .....44.1kHz Item S/N ratio THD + N1 Measurement conditions EIAJ (with "A" weighting filter) EIAJ (0dB) EIAJ (-1dB) EIAJ (-10dB) Dynamic range Channel separation Level difference between channels ADC input level2 Output level3 Analog current consumption 1 See Graph 1. 2 Input level to the ADC which outputs FS. (= prefilter output level) 3 Prefilter gain = -3.52dB EIAJ Min. 82 Typ. 92 0.1 0.02 0.013 91 95 0.1 1.33 1.0 27 0.03 dB dB dB Vrms Vrms mA % Max. Unit dB
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CXD2721Q-1
2. DAC Characteristics Characteristics using the measurement circuit in Fig. 2, including the built-in post filter. Unless otherwise specified, the measurement conditions are as given below. * DATA ....0dB (= FS), 1kHz, 16bit * fs ...........44.1kHz Item S/N ratio THD + N Dynamic range Channel separation Measurement conditions EIAJ (with "A" weighting filter) EIAJ (0dB) EIAJ (-1dB) EIAJ (-60dB) EIAJ Min. Typ. 97 0.009 0.005 94 118 0.05 1.11 Max. Unit dB % dB dB dB Vrms
Level difference between channels EIAJ Output level EIAJ
3. Filter Characteristics Block Prefilter Item Feedback resistance value Maximum amplification ratio (100kHz or less) Load resistance value Cut-off frequency (= fc) 10 90 Min. 10 20 Typ. Max. Unit k dB k kHz
Post filter
1.00
THD + N [%]
0.10
0.01
-60
-50
-40
-30
-20
-10
0 10 (2Vrms)
Analog input level [dB]
Graph 1.
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CXD2721Q-1
CXD2721Q-1 (Master mode) 22k LOx NE5532 IN 10 R 33k 15k 330p 100p AOUTx AINx 100k 10k 10k 470p 220p NE5532 10k 1500p NE5532 10 10k 330k OUT
470p
CH R
AD1 (= open)
AD2 (= open)
AD3 1M
Unit
Fig. 1. ADC + DAC Measurement Circuit
CXD2721Q-1 (Slave mode) 48fs fs (= 44.1kHz) DATA 1500p NE5532 10 10k 220p 330k OUT
BCK LRCK AOUTx 10k SI
470p 10k
NE5532 10k
470p
Fig. 2. DAC Measurement Circuit
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CXD2721Q-1
Description of Functions 1. Master/Slave Modes [Relevant pins] XMST, LRCK, BCK When connecting multiple CXD2721Q-1 or when using this LSI as a pair with a DA converter such as the CXD2558M, one of the CXD2721Q-1 should be set to master mode to supply LRCK and BCK. The clock applied to LRCK and BCK in slave mode must be synchronized to either the crystal oscillator clock of the XTLI and XTLO pins or the external clock input from the XTLI pin. XMST H L Mode Slave mode Master mode LRCK, BCK I/O Input Output
Table 1-1. LRCK, BCK Mode Setting
2. Master Clock System [Relevant pins] XTLI, XTLO, BFOT, BSL1, BSL2 768fs (fs = 44.1kHz) is assumed for the master clock system and the connection is as shown below. BFOT outputs the clock obtained by frequency dividing the master clock. The frequency division ratio can be changed by BSL1 and BSL2. BSL2 0 0 1 1 BSL1 0 1 0 1 BFOT 384fs 768fs 256fs 512fs
(1) Master
(2) Slave
BFOT O 256fs/384fs/512fs/768fs 512fs I BSL1 I BSL2 Frequency divider
I XTLI
768fs
Frequency divider
512fs
O OPEN XTLO
I XTLI O XTLO 768fs
Fig. 2-1.
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CXD2721Q-1
3. Reset Circuit [Relevant pins] XRST, XTLI, XTLO This LSI must be reset after the power is turned on. Reset is performed by setting the XRST pin Low for 1/Fs or more after the supply voltage satisfies the recommended operating condition, and the crystal oscillator clock of the XTLI and XTLO pins or the external clock input from the XTLI pin is correctly applied. 4. Serial Audio Interface (SIF) [Relevant pins] SI, SO, BCK, LRCK, XS24, XMST Serial data is used for the external communication of the digital audio data. The CXD2721Q-1 has one system each for input and output, and each system inputs/outputs 2 channels of data per 1 sampling cycle. Either the 32-bit clock mode or the 24-bit clock mode can be selected. In master mode, the setting is fixed to 32-bit clock mode. (1) Pin Configuration The pins shown in the table below are assigned to the SIF. Symbol SI SO BCK LRCK XS24 XMST I/O I O I/O I/O I I Serial input; taken synchronized to BCK. Serial output; output synchronized to BCK. BCK I/O; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output supports 32-bit clock mode only. LRCK I/O (1fs). SI0 slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot. Valid only in slave mode. BCK, LRCK master mode/slave mode switching input. Low: master mode; High: slave mode. Table 4-1. Pin Configuration Function
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CXD2721Q-1
(2) Operating Modes LRCK/BCK mode and SI/SO system settings can be selected by the setup register settings as follows. LRCK/BCK Mode Settings
Setup register SQ11 SQ10 SQ09
Function
Contents
LRCK format "0": normal, "1": IIS LRCK polarity selection "0": Lch "H", "1": Lch "L" BCK polarity selection relative to LRCK edge "0": edge , "1": edge Table 4-2. LRCK/BCK Mode Settings
SI/O System Register Settings SI system Setup register SQ08 SQ07 SQ06 SQ05 Function SI data order SI frontward/rearward truncation SI data word length SI data word length Contents "0": MSB first, "1": LSB first "0": Frontward truncation, "1": Rearward truncation SQ06 SQ05 0 0 : 16 bits 0 1 : 18 bits 1 0 : 20 bits 1 1 : 24 bits
Table 4-3. SI System Register Settings
SO system Setup register SQ04 SQ03 SQ02 SQ01 Function SO data order SO frontward/rearward truncation SO data word length Contents "0": MSB first, "1": LSB first "0": Frontward truncation, "1": Rearward truncation SQ02 SQ01 0 0 : 16 bits 0 1 : 18 bits 1 0 : 20 bits 1 1 : 24 bits
Table 4-4. SO System Register Settings
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CXD2721Q-1
(3) SIF Format The serial interface has one input/output system each, and except for the slot number, the following formats can be set independently for the input and output systems by setting the setup register. The serial interface can also be made to support IIS format, to enable connection to Philips and other devices. The timing charts for each data format are shown on pages 18 and 19. 32-bit slot (XS24 = High) Setup register SI format MSB first MSB first MSB first MSB first MSB first LSB first LSB first LSB first LSB first 16 bits 18 bits 20 bits 24 bits 16 bits 16 bits 18 bits 20 bits 24 bits Frontward truncation Frontward truncation Frontward truncation Frontward truncation Rearward truncation Rearward truncation Rearward truncation Rearward truncation Rearward truncation SQ05 SQ06 SQ07 SQ08 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1
Table 4-5. 32-bit Slot Serial IN
Setup register SO format MSB first MSB first MSB first MSB first MSB first LSB first 16 bits 18 bits 20 bits 24 bits 24 bits 24 bits Rearward truncation Rearward truncation Rearward truncation Rearward truncation Frontward truncation Rearward truncation
SQ01 SQ02 SQ03 SQ04 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1
Table 4-6. 32-bit Slot Serial OUT
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CXD2721Q-1
24-bit slot (XS24 = Low) Setup register SI format MSB first MSB first MSB first MSB first MSB first LSB first LSB first LSB first LSB first 16 bits 16 bits 18 bits 20 bits 24 bits 16 bits 18 bits 20 bits 24 bits Rearward truncation Frontward truncation Frontward truncation Frontward truncation Rearward truncation Rearward truncation Rearward truncation SQ05 SQ06 SQ07 SQ08 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1
Table 4-7. 24-bit Slot Serial IN
Setup register SO format MSB first MSB first MSB first MSB first LSB first 16 bits 18 bits 20 bits 24 bits 24 bits Rearward truncation Rearward truncation Rearward truncation
SQ01 SQ02 SQ03 SQ04 0 1 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1
Table 4-8. 24-bit Slot Serial OUT
Note) means "don't care".
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Digital Audio Data Input Timing (with polarities: SQ11 = 0, SQ10 = 0, SQ09 = 0)
32bit slot Lch Rch
LRCK
BCK
Invalid 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Invalid
* MSB first 16 bits frontward truncation LSB
Invalid 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Invalid
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB * MSB first 24 bits frontward truncation LSB MSB
Invalid
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB * MSB first 16 bits rearward truncation LSB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SI MSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Invalid
Invalid
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
MSB
LSB
* LSB first 16 bits rearward truncation
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Invalid
LSB
Invalid
MSB
LSB
MSB
* LSB first 24 bits rearward truncation
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Invalid
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
LSB
MSB
LSB
MSB
- 18 -
Lch
13 12 11 10 09 08 07 06 05 04 03 02 01 00 Invalid 15 14 13
24bit slot LRCK
Rch
BCK
* MSB first 16 bits rearward truncation
12 11 10 09 08 07 06 05 04 03 02 01 00
Invalid
15
14
MSB * MSB first 16 bits frontward truncation
05 15 14 04 03 02 01 00 Invalid 13 12
LSB
11 10 09 08
MSB
07 06 05 04 03 02 01 00 Invalid
LSB
15
14
13
12
11
10
09
08
07
06
SI
13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB * MSB first 24 bits
23
LSB
MSB
22 21 20 19 18 17 16 15 14 13 12 11 10 09
LSB
08 07 06 05 04 03 02 01 00
23
22
21
20
19
18
17
16
15
14
MSB * LSB first 16 bits rearward truncation
02 03 04 05 06 07 08 09 10 11 12 13 14
LSB MSB
15 Invalid 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
LSB
15
Invalid
00
01
MSB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 01 02 03 04 05 06 07
LSB
08 09 10 11 12 13 14 15 16 17 18 19 20 21 22
MSB
23
* LSB first 24 bits MSB LSB MSB
00
01
02
03
04
05
06
07
08
09
LSB
CXD2721Q-1
Fig. 4-1.
Digital Audio Data Output Timing (with polarities: SQ11 = 0, SQ10 = 0, SQ09 = 0)
32bit slot Lch Rch
LRCK
BCK
* MSB first 16 bits rearward truncation
14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
15
* MSB first 18 bits rearward truncation
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 17
MSB LSB MSB MSB
19
LSB LSB LSB LSB
" 0 " truncation
17
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB * MSB first 20 bits rearward truncation LSB LSB
23 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
19
18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SO LSB
" 0 " truncation
MSB * MSB first 24 bits rearward truncation MSB MSB
23
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
* MSB first 24 bits frontward truncation
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB LSB MSB
" 0 " truncation
LSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
* LSB first 24 bits rearward truncation MSB LSB MSB
" 0 " truncation
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
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Lch
13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13
LSB
24bit slot LRCK
Rch
BCK
* MSB first 16 bits rearward truncation
12 11 10 09 08 07 06 05 04 03 02 01 00
15
14
MSB * MSB first 18 bits rearward truncation LSB
13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
LSB
00
17
16
15
14
MSB * MSB first 20 bits rearward truncation LSB
13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
LSB
00
SO
13 12 11 10 09 08 07 06 05 04 03 02 01
19
18
17
16
15
14
MSB * MSB first 24 bits
LSB
00 23 22 21
MSB
20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
LSB
00
23
22
21
20
19
18
17
16
15
14
MSB
10 11 12 13 14 15 16 17 18 19 20 21
LSB MSB
22 23 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22
LSB
23
* LSB first 24 bits MSB LSB MSB
00
01
02
03
04
05
06
07
08
09
LSB
CXD2721Q-1
Fig. 4-2.
CXD2721Q-1
5. Microcomputer Interface [Relevant pins] RVDT, TRDT, SCK, XLAT, REDY The CXD2721Q-1 performs the serial audio interface format setting and coefficient settings such as volume and microphone echo delay amount by serial data from the microcomputer. Further, bidirectional communication such as internal data read from the CXD2721Q-1 to the microcomputer can be performed at the rate of once per 1 LRCK. (1) Pin Configuration The five external pins indicated in the table below are assigned to the microcomputer interface. The microcomputer interface begins operation when XLAT is received, so multiple CXD2721Q-1 can be used by connecting RVDT, TRDT, SCK and REDY in common and controlling (wiring) only XLAT separately. Symbol RVDT TRDT I/O I O Serial data input from microcomputer. Serial data output to the microcomputer. High impedance status unless this pin is set to internal data read status by the microcomputer. Therefore, pull-up or pull-down should be performed so that the potential is not unstable when this pin is not active. Shift clock for serial data. Input data from RVDT is taken according to the SCK rise, and output data from TRDT is sent out according to the SCK fall. Interprets the 8 bits of RVDT before this signal rises as transfer mode data, and the bits before that as address data. Transfer prohibited when Low level. Transfer enabled when High. This pin is an open drain, and must be pulled up externally. Table 5-1. Microcomputer Interface External Pins Function
SCK XLAT REDY
I I O
- 20 -
CXD2721Q-1
(2) Description of Communication Formats The data transfer timing between the microcomputer interface and the coefficient RAM and setup register is called the SV cycle, and is generated once per 1 LRCK. The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect on signal processing, and there is no risk of the sound being cut. In read/write modes, Address section + Mode section + Data section act as one package of data to perform data transfer between the microcomputer and the CXD2721Q-1. [Write] * For coefficient RAM
Address section (8 bits) Mode section (8 bits) RVDT A0 A7 M0 M7 Data section (16 bits) D0 D15
SCK
XLAT
REDY
TRDT
[Read] * For coefficient RAM
Address section (8 bits) Mode section (8 bits) RVDT A0 A7 M0 M7
SCK
XLAT
REDY Data section (16 bits) TRDT D0 D15
Note) For both read and write, the data section is 24 bits for the setup register. Fig. 5-1. Examples of Communication
- 21 -
CXD2721Q-1
(3) Data Structure The data structure is classified into three types as shown in the table below. All data communication is performed with LSB first. Symbol A0 to A7 M0 to M7 D0 to D15/SQ00 to SQ23 Bit length 8 8 16/24 Contents Address section Transfer mode section Data section Table 5-2. Data Structure Coefficient RAM is 16 bits; setup register is 24 bits Remarks
(3)-1. Transfer Mode Section The transfer mode section is 8 bits and has the following functions. Bit M7 M6 M5 M4 M3 M2 M1 M0 VRD VS1 Data type VS0 Reserve Receive/Send 0: Receive 1: Send Note) Polarity as seen from the CXD2721Q-1 Symbol XVMT SO Mute Reserve VS1 0 1 VS0 0 0 0: ON (No sound) 1: OFF Function
Setup register (Setup Register) Coefficient RAM (K-RAM)
Table 5-3. Transfer Mode Section
(3)-2. Address Section The coefficient RAM has a 192-word structure, so the address section is 8 bits. The setup register has a 1word structure, so the address section data may be optional. (3)-3. Data Section The coefficient RAM has a 16-bit structure (D0 to D15), so 16 SCK are required. The setup register has a 24bit structure (SQ00 to SQ23), so 24 SCK are required.
- 22 -
CXD2721Q-1
(4) Details of Communication Methods The definitions of signal timing required for control from the microcomputer are given below. (4)-1. Write First, address and mode section data are sent from the microcomputer, synchronized with SCK, to the RVDT pin. The address section data is 8 bits for both the coefficient RAM and setup register. The setup register has a 1word length, so optional data can be transferred. Address section data is transferred with LSB first. Mode section data is fixed at 8 bits regardless of the transfer contents. The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions: * RV data must be established before SCK rises (tDS 20ns). * RV data must be held for 1t + 20ns or more after SCK rises (tDH). SCK itself has the following restrictions: * SCK Low level must be 1t + 20ns or more (tSWL). * SCK High level must also be 1t + 20ns or more (tSWH). After SCK rises, which corresponds to the final mode section data, XLAT rises (tSLP 20ns). The XLAT Low level width must be maintained at 1t + 20ns or more (tLWL). Further, fall timing restrictions are: * For the preceding transfer, if REDY falls due to SCK, as for write, 3t + 20ns or more is required (tSLD). * For the preceding transfer, if REDY falls due to XLAT, as for read, 20ns or more is required (tLDR). Further, if preceding transfers have been performed and REDY = Low, XLAT must wait for REDY = High before rising. The procedure until this point is the same for write and read.
D0/SQ00 RVDT A0 tDS SCK tSWL XLAT tSLD or tLWH REDY tLDR TRDT High-Z tRLP tLWL tSWH tSLP tLSD A7 M0 tDH M7 SQ00
D15/SQ23 SQ23 A0 tSS M7
tBSP
tSLP
tSLD tSBD tLDR tRLP
Fig. 5-2. Write Timing
- 23 -
CXD2721Q-1
Data section write begins after XLAT rises, and here also transfer must be performed with LSB first, with tDS and tDH restrictions. In addition, after XLAT rises at the starting point for sending to the data section, wait for 3t + 20ns or more for the first SCK rise (tLSD). When 16 bits (coefficient RAM) or 24 bits (setup register) of this write is repeated, REDY goes Low within 4t + 50ns, and the microcomputer is informed of waiting status for the SV cycle, which is the dedicated data rewrite cycle, by the microcomputer interface (tSBD). When REDY goes High again, the corresponding data is written. The next communication can be restarted by using the REDY signal as follows. * When REDY = Low, SCK can rise for the next transfer (tBSP 20ns). * Similarly, when REDY = Low, XLAT can fall for the next transfer (tLDR 20ns). REDY will fall due to this communication, but it is prohibited for XLAT to rise for the next transfer before REDY rises. Be sure that the next XLAT rises after REDY rises (tRLP 20ns). In order to restart the next transfer without using the REDY signal, the following conditions must be observed. * There should be 2t + 40ns or more left between the SCK rise for the final data section and the SCK rise for the next transfer (tSS). * Similarly, XLAT can fall for the next transfer after waiting 3t + 20ns or more after the final data section SCK rise (tSLD). The tSS and tSLD here are shorter times than tSBD 4t + 50ns, so these are rather loose restrictions. However, even in this case the XLAT rise for the next transfer must come after REDY rises (tRLP 20ns). Further, the restriction for the XLAT fall at the starting point of this write from tSLD can be: * tSLD 3t + 20ns if the preceding transfer was "write".
- 24 -
CXD2721Q-1
(4)-2. Read First, address and mode section data are transferred synchronized to SCK, and XLAT rises together with this. The procedure until this point is the same as for write, so the description is omitted here. Read differs from write in that after XLAT rises, REDY falls within 3t + 50ns (tLBD), and the microcomputer is informed of SV cycle waiting. At this time, the TRDT pin changes from high-impedance status to active status (tLDN 3t + 80ns) simultaneously with the fall of REDY. When the read data is ready, the REDY pin changes from Low to High. When the data read out from the TRDT pin is made TR, and SCK falls (tRSDP 20ns) when the REDY pin goes High, the first TR data is established within 2t + 70ns (tSDD). The microcomputer reads this data at the SCK rise. The TR data is read in order from the LSB with 16 bits for the coefficient RAM and 24 bits for the setup register by adding SCK. When all the corresponding data is read, read is completed. Next, the method for restarting transfer after read is completed is described. As in Case 1, there is a method for sending address and mode section data consecutively after reading all of the 16- or 24-bit data. 2t + 40ns or more should be left between the SCK rise for the final data read and the next SCK rise (tSS), and this is established by the conditions tSWL 1t + 20ns and tSWH 1t + 20ns. Further, at this read REDY changes from High to Low, but it is prohibited for the XLAT for the next transfer to fall before this. If REDY = Low has been established, XLAT can fall (tLDR 20ns). Also, while 16- or 24-bit data is being read from the TRDT pin, address and mode section data writing to the RVDT pin for the next transfer can be started. In Case 3, the final section of read data and the final data in the mode section overlap, and this allows shifting to the next transfer processing in the shortest possible time after data read. It is also possible to have data read and address and mode section write overlap partially, as shown by Case 2.
- 25 -
CXD2721Q-1
RVDT SCK
A0 tDS tSWL
A7 tDH
M0
M7
A0
A1
M7
tSWH
XLAT tSLD or tLWH REDY tLDR TRDT
tSLP tLWL tLBD tLDN tRLP tSDD
tRSDP
tSS tLDR
tSLP
tSDD SQ00 D0/SQ00
tSDD SQ22
tSDF SQ23
case 1
D14/SQ22 D15/SQ23
RVDT SCK
A0 tDS tSWL
A7 tDH
M0
M7
A5
A6
M7
tSWH
XLAT tSLD or tLWH REDY tLDR TRDT
tSLP tLWL tLBD tLDN tRLP tSDD
tRSDP
tSS tLDR
tSLP
tSDD SQ00 D0/SQ00
tSDD SQ22
tSDF SQ23
case 2
D14/SQ22 D15/SQ23
RVDT SCK
A0 tDS tSWL
A7 tDH
M0
M7
M7
tSWH
XLAT tSLD or tLWH REDY tLDR TRDT
tSLP tLWL tLBD tLDN tRLP tSDD
tRSDP tLDR tSDD SQ00 D0/SQ00 tSDD SQ22
tSLP
SQ23
case 3
D14/SQ22 D15/SQ23
Fig. 5-3. Read Timing
- 26 -
CXD2721Q-1
6. Setup Register When the setup register is selected in the microcomputer interface transfer mode, the following settings are possible for the serial audio interface and DAC. Data section bit SQ23 to 14, Reserve bit SQ12 SQ13 SQ11 SQ10 SQ09 DAC output selection LRCK format LRCK polarity selection BCK polarity selection relative to LRCK edge SI data order Control Must be Low for setup register settings to change 0: Built-in LPF used 1: External LPF used (PWM output) 0: Normal 1: IIS 0: Lch High 1: Lch Low 0: Falling edge 1: Rising edge 0: MSB first 1: LSB first (24-bit rearward truncation only) When system reset is Low All Low Built-in LPF Normal Lch High Falling edge
SQ08
MSB first
SQ07
SI frontward/rearward truncation
0: Frontward truncation (valid only for MSB first/24 bits/32 slots) Frontward truncation 1: Rearward truncation SQ06 0 0 1 1 SQ05 0: 16 bits 1: 18 bits 0: 20 bits 1: 24 bits
SQ06, 05
SI data word length
16 bits
SQ04 SQ03
SO data order SO frontward/rearward truncation
0: MSB first 1: LSB first 0: Frontward truncation 1: Rearward truncation SQ02 0 0 1 1 0: ON 1: OFF Table 6-1. SQ01 0: 16 bit 1: 18 bit 0: 20 bit 1: 24 bit
LSB first Frontward truncation
SQ02, 01
SO data word length
16 bits
SQ00
DAC forced mute
ON
- 27 -
CXD2721Q-1
7. Coefficient RAM Settings When the coefficient RAM is selected in the microcomputer interface transfer mode, Karaoke mode or music mode can be selected and coefficient parameters such as each section's volume and microphone echo delay amount can be set. Coefficient RAM addresses other than those given in these specifications are "don't care". 7-1. Mode Settings [Relevant coefficients] SW1 (address = 10H), SW2 (address = 18H), SW3 (address = 78H) The CXD2721Q-1 functions include Karaoke mode which consists mainly of Karaoke applications and music mode which consists mainly of surround functions. Karaoke mode is further divided into two modes by the delay RAM assignment, and the delay amount can be changed by varying the microphone echo and surround decimation ratios (only for Karaoke mode). The settings for each mode are as follows. Setting item Mode Karaoke mode 0 Karaoke mode 1 Music mode SW1 (10H) 0000H 0000H 8000H SW2 (18H) 0000H 8000H -- Key control for accompaniment 32K bits 56K bits -- Key control for voice 8K bits 8K bits -- -- Microphone echo 64K bits 64K bits 128K bits Surround 24K bits
Fig. 7-1-1. Operating Modes and Built-in Delay RAM Assignments
Setting item Mode Karaoke mode 0 Karaoke mode 0 Karaoke mode 1 Karaoke mode 1
Microphone echo SW1 SW2 SW3 Maximum (10H) (18H) (78H) Decimation Band ratio (kHz) delay (ms) 0000H 0000H 0000H 0000H 0000H 8000H 0000H 8000H 0000H 0000H 8000H 8000H -- -- 1/2 1/3 1/2 1/3 -- Approxi- Approximately 8 mately 185 Approxi- Approximately 6 mately 278 Approxi- Approximately 8 mately 1851 Approxi- Approximately 6 mately 2781 -- --
Surround Decimation ratio 1/1 1/1 1/2 1/3 1/1 Band (kHz) Maximum delay (ms)
ApproxiApproximately 20 mately 35 ApproxiApproximately 20 mately 35 Approxi- Approximately 8 mately 1851 Approxi- Approximately 6 mately 2781 Approxi- Approximately 20 mately 185
Music mode 8000H
1 The microphone echo and surround decimation ratios can be selected in Karaoke mode 1, and the maximum delay amount of approximately 185ms for 1/2 decimation and approximately 278ms for 1/3 decimation can be divided as desired between microphone echo and surround. For example, if a delay of 200ms is assigned to microphone echo with 1/3 decimation, the surround delay amount is 78ms. Fig. 7-1-2. Operating Modes and Microphone Echo/Surround Settings
- 28 -
CXD2721Q-1
7-2. Karaoke Mode Karaoke mode simultaneously provides key control, voice cancellation, microphone echo, voice pitch shifter, voice PEQ, simple surround and other functions. (1) Fixed Values for System Initialization When the system is initialized, the coefficient RAM must be set to the fixed values shown below for internal operation. Address 01H 02H 03H 10H 13H 14H 15H 16H 17H 1AH 1CH 20H 21H 27H 28H 2DH 30H 31H 32H 33H 34H 35H 36H 37H 38H Fixed value 68A9H 5121H 0000H 0000H 8B2AH 3BF7H 38DFH 4E77H 2E90H 0000H 4000H 0010H 4000H 8000H 0000H 0008H 0000H 0000H 8000H 0000H 0000H 0000H 0000H 0000H 8000H Address 3CH 48H 49H 4AH 4BH 4CH 4DH 52H 58H 6BH 79H 7AH 7CH 7DH 7EH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H Fixed value 0000H 2000H 0B00H 1500H 1FF0H 8000H 0000H 0008H 82EAH 8000H 5555H 0000H AAAAH 0008H 0010H 0092H 0209H 02CDH 0109H FDA0H FD19H 0189H 058AH 016DH F7BEH Address A5H A6H A7H A8H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH Fixed value F72AH 0A4EH 2706H 34EEH 6000H FF80H 00A1H 016EH 01F8H 0193H 0024H FE70H FDBAH FED8H 015AH 037FH 0344H FFFFH FB5CH F8E3H FBF6H 0575H 129CH 1E0DH 2294H
Table 7-2-1. Coefficient Setting Values for Karaoke Mode Initialization
Note) Consult your Sony representative with regard to use at other than fs = 44.1kHz, as the fixed values change.
- 29 -
CXD2721Q-1
(2) Setting Data The relationships between the coefficient RAM and each function during DSP operation are as follows. Address Symbol 00H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 18H 19H 1BH 1EH 22H 23H 24H 25H 26H 2EH 3BH 3DH 3EH 3FH 40H 41H 42H 43H 44H Ki Ke DC1a1 DC1a0 DC1b KisLm KisRc KiaLm KiaRc KisRm KisLc KiaRm KiaLc SW1 PL PR SW2 Kvc TRi TVi nRpR KWR KRigh KLeft KWR-1 Ks Kimc DC2a1 DC2a0 DC2b PEQa PEQb1 PEQb2 PEQg HCa1 Function SI data input level control De-emphasis ON/OFF DC cut1 coefficient for accompaniment DC cut1 coefficient for accompaniment DC cut1 coefficient for accompaniment SI CH1 data Lch mix SI CH2 data Lch mix ADC CH1 data Lch mix ADC CH2 data Lch mix SI CH2 data Rch mix SI CH1 data Rch mix ADC CH2 data Rch mix ADC CH1 data Rch mix Karaoke/music mode switch Panpot volume for voice cancellation Panpot volume for voice cancellation Karaoke mode 0/1 switch Voice cancellation ON/OFF Key control setting value for accompaniment Key control setting value for voice Pitch ratio for accompaniment Key control setting value for accompaniment Key control setting value for accompaniment Key control setting value for accompaniment Key control setting value for accompaniment Key control ON/OFF for accompaniment Microphone input level control DC cut2 coefficient for voice DC cut2 coefficient for voice DC cut2 coefficient for voice PEQ coefficient for voice PEQ coefficient for voice PEQ coefficient for voice PEQ coefficient for voice High cut1 coefficient for voice Setting value See Table 7-2-9 ON = ac19H OFF = 0000H See Table 9-1 See Table 9-1 See Table 9-1 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 Karaoke mode=0000H,Music mode=8000H See Table 7-2-3 See Table 7-2-3 Mode 0 = 0000H; mode 1 = 8000H ON = 8000H OFF = 0000H See Table 7-2-5 See Table 7-2-5 See Table 7-2-4 See Table 7-2-5 See Table 7-2-5 See Table 7-2-5 See Table 7-2-5 ON = 8000H OFF = 0000H See Table 7-2-9 See Table 9-1 See Table 9-1 See Table 9-1 See Table 9-4 See Table 9-4 See Table 9-4 See Table 9-5 See Table 9-2
Table 7-2-2 (1). Coefficient RAM Setting Data for Karaoke Mode (1/3) Note) See "8. DSP Signal Flow" regarding the symbols. - 30 -
CXD2721Q-1
Address Symbol 45H 46H 47H 53H 54H 55H 56H 59H 5AH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 65H 66H 67H 68H 69H 6AH 6EH 6FH 71H 73H 74H 75H 76H 77H 78H 81H 82H 83H HC1a0 HC1b VnRpR Krmd Krmpd Krme Krmpe Kdryd Keffd KLmd KRmd KLsd KRsd KLod KRod Kdrys Keffs KLms KRms KLss KRss KLos KRos Tdoe Kre Tre Krd Kfb HC2a1 HC2a0 HC2b SW3 KLri KRri Kfbs
Function High cut1 coefficient for voice High cut1 coefficient for voice Pitch ratio for voice High cut1 output mix for voice Direct sound Pitch shifter output mix for voice Direct sound High cut1 output mix for voice Echo input Pitch shifter output mix for voice Echo input Voice system direct sound DAC side mix Microphone echo sound DAC side mix Key control output DAC side Lch mix for accompaniment Key control output DAC side Rch mix for accompaniment Surround output DAC side Lch mix Surround output DAC side Rch mix System volume DAC side Lch System volume DAC side Rch Voice system direct sound serial out side mix Microphone echo sound serial out side mix
Setting value See Table 9-2 See Table 9-2 See Table 7-2-4 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9
Key control output serial out side Lch mix for accompaniment See Table 7-2-9 Key control output serial out side Rch mix for accompaniment See Table 7-2-9 Surround output serial out side Lch mix Surround output serial out side Rch mix System volume serial out side Lch System volume serial out side Rch Microphone echo delay amount Microphone echo read tap volume Microphone echo read tap address Microphone echo input sound mix Microphone echo reverberation sound mix High cut2 coefficient for microphone echo High cut2 coefficient for microphone echo High cut2 coefficient for microphone echo 1/2, 1/3 decimation mode switch Surround input Lch mix Surround input Rch mix Surround reverberation sound mix See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-9 See Table 7-2-6 See Table 7-2-9 See Table 7-2-6 See Table 7-2-9 See Table 7-2-9 See Table 9-3 See Table 9-3 See Table 9-3 1/2 mode = 0000H; 1/3 mode = 8000H See Table 7-2-9 See Table 7-2-9 See Table 7-2-9
Table 7-2-2 (2). Coefficient RAM Setting Data in Karaoke Mode (2/3) Note) See "8. DSP Signal Flow" regarding the symbols. - 31 -
CXD2721Q-1
Address Symbol 84H 85H 86H 87H 88H 89H 8AH 8DH 8EH 8FH 90H 91H 92H 93H 94H HDmp KLtp1 KLtp2 KLtp3 KRtp1 KRtp2 KRtp3 Tdis TpL1 TpL2 TpL3 TpR1 TpR2 TpR3 Tdos
Function High dump coefficient for surround Read tap volume Lch 1 for surround Read tap volume Lch 2 for surround Read tap volume Lch 3 for surround Read tap volume Rch 1 for surround Read tap volume Rch 2 for surround Read tap volume Rch 3 for surround Delay RAM setting value for surround Read tap address Lch 1 for surround Read tap address Lch 2 for surround Read tap address Lch 3 for surround Read tap address Rch 1 for surround Read tap address Rch 2 for surround Read tap address Rch 3 for surround Surround delay amount
Setting value See Table 9-6 See Tables 7-2-9 and 7-2-11 See Tables 7-2-9 and 7-2-11 See Tables 7-2-9 and 7-2-11 See Tables 7-2-9 and 7-2-11 See Tables 7-2-9 and 7-2-11 See Tables 7-2-9 and 7-2-11 See Table 7-2-7 See Table 7-2-8 See Table 7-2-8 See Table 7-2-8 See Table 7-2-8 See Table 7-2-8 See Table 7-2-8 See Table 7-2-8
Table 7-2-2 (3). Coefficient RAM Setting Data in Karaoke Mode (3/3) Note) See "8. DSP Signal Flow" regarding the symbols.
7-2-1. Voice Canceller Settings [Relevant coefficients] PL (address = 11H), PR (address = 12H), KVC (address = 19H) The vocal sound set at the center can be canceled by setting KVC = 8000H and PL, PR = 7000H. Voice cancelling at other than the center setting can be performed by the panpot volumes. Panpot volume values are PL for CH1 and PR for CH2, and at the center position they are both 0.857. To turn off the voice canceller, set KVC = 0000H and PL, PR = 0000H. PL and PR setting values are hexadecimal notation with D15 as MSB and D0 as LSB. PL 7000H 7000H 7000H 7000H 7000H 7000H 7000H 7000H PR 7000H 6000H 5000H 4000H 3000H 2000H 1000H 0000H CH2 Setting position Center PL 7000H 6000H 5000H 4000H 3000H 2000H 1000H 0000H PR 7000H 7000H 7000H 7000H 7000H 7000H 7000H 7000H CH1 Setting position Center
Table 7-2-3. Settings for Voice Canceller Panpot Volumes
- 32 -
CXD2721Q-1
7-2-2. Key Controller Settings [Relevant coefficients] TRi (address = 1BH), TVi (address = 1EH), nRpR (address = 22H), KWR (address = 23H), KRigh (address = 24H), KLeft (address = 25H), KWR-1 (address = 26H), Ks (address = 2EH), VnRpR (address = 47H), Krmpd (address = 55H), Krmpe (address = 56H) (1) Key Controller Pitch Ratio nRpR (D15, ..., D2) is 2's complement format with the decimal point between D14 and D13, and sets the desired pitch ratio directly. (VnRpR has the same type of setting as nRpR.) nRpR = Dn x 2n-14
n=2 15
The expression range for the pitch ratio is: -2.0 nRpR 2.0 -2-12 but for practical use it is: -0.5 nRpR 1.0 or 1 octave Use within a range of half an octave is recommended for quality of sound, although this depends on the aim and the source. Also, the algorithm is such that allophones are not generated even when the nRpR setting value is changed. (2) Notes on Key Controller OFF The pitch does not change when nRpR and VnRpR are set to 0000H (OFF) when the key controller is OFF, but depending on the internal status during OFF, there is no guarantee that the input value will be output as is. During OFF, after setting nRpR and VnRpR to 0000H (OFF), set the pitch control section to through status with the following settings. Accompaniment controller OFF: Ks = 0000H (OFF) Voice key controller OFF : Krmpd = 0000H (OFF) : Krmpe = 0000H (OFF)
- 33 -
CXD2721Q-1
(3) Pitch Ratio Setting Examples Pitch ratio setting examples are illustrated below. Setting values nRpR are hexadecimal notation with D15 as MSB and D2 as LSB for a total of 14 bits. (D1 and D0 can be optional data.) CENT 0 +50 +100 +150 +200 +250 +300 +350 +400 +450 +500 +550 +600 +650 +700 +750 +800 +850 +900 +950 +1000 +1050 +1100 +1150 +1200 nRpR 0000H 01E0H 03CEH 05CAH 07D6H 09F1H 0C1BH 0E56H 10A2H 12FFH 156EH 17EEH 1A82H 1D29H 1FE4H 22B3H 2597H 2892H 2BA2H 2EC9H 3208H 3560H 38D0H 3C5BH 4000H CENT 0 -50 -100 -150 -200 -250 -300 -350 -400 -450 -500 -550 -600 -650 -700 -750 -800 -850 -900 -950 -1000 -1050 -1100 -1150 -1200 nRpR 0000H FE2EH FC69H FAB1H F905H F765H F5D2H F44AH F2CCH F15AH EFF3H EE95H ED42H EBF8H EAB8H E980H E852H E72CH E60EH E4F9H E3ECH E2E6H E1E8H E0F1H E000H
Table 7-2-4. Pitch Ratio Setting Examples The numeric representation format for pitch ratio here is: nRpR = Dn x 2n-14
n=2 15
The numeric representation range is: -2.0 nRpR 2.0 -2-12 Also, the relationship formula with music word cent value C is: nRpR = 2
C 1200
-1, C = 1200 log2 [nRpR + 1] [cent]
The semitone at the average ratio is 100 [cent]. - 34 -
CXD2721Q-1
(4) Key Controller Settings for Each Karaoke Mode The CXD2721Q-1 must perform the following coefficient settings for the Karaoke mode 0/1 selection. Setting coefficient Mode Karaoke mode 0 Karaoke mode 1 SW1 0000H 0000H SW2 0000H 8000H TRi 2000H 3800H TVi 4000H 7000H KWR 4000H 7000H KRigh 1600H 2C00H KLeft 2A00H 4400H KWR-1 3FF0H 6FF0H
Table 7-2-5. Key Controller Setting Values
7-2-3. Microphone Echo Delay Amount Setting [Relevant coefficients] Tdoe (address = 6EH), Tre (address = 71H) The microphone echo delay amount can be varied by setting the coefficient Tdoe (12 bits from D14 to D3) value. The relationships between the coefficient and the delay amount are shown in Table 7-2-6. Coefficient Tre (12 bits from D14 to D3) is the microphone input echo initial delay time. Set in the range of 0008H to Tdoe. Delay (fs = 44.1kHz) Setting value Tdoe 0008H 0010H 0018H * * * * 7FF0H 7FF8H 1/2 decimation 0.045ms * * * * * * * 185.714ms 1/3 decimation 0.068ms * * * * * * * 278.571ms
4095 steps
Approximately 0.045ms/step setting possible
Approximately 0.068ms/step setting possible
Table 7-2-6. Microphone Echo Delay Amount Setting
- 35 -
CXD2721Q-1
7-2-4. Surround (Karaoke Mode) Coefficient Settings [Relevant coefficients] Tdoe (address = 6EH), Tdis (address = 8DH), TpL1 (address = 8EH), TpL2 (address = 8FH), TpL3 (address = 90H), TpR1 (address = 91H), TpR2 (address = 92H), TpR3 (address = 93H), Tdos (address = 94H) (1) Karaoke Mode 0/1 Setting Values The surround settings for Karaoke mode 0/1 are as follows. Setting coefficient Mode Karaoke mode 0 (1/1 decimation) Karaoke mode 1 (1/2 decimation) Karaoke mode 1 (1/3 decimation) SW1 0000H 0000H 0000H SW2 0000H 8000H 8000H SW3 -- 0000H 8000H Tdis 5000H Tdoe Tdoe - 0008H
Table 7-2-7. Surround Karaoke Mode 0/1 Setting Values
(2) Delay Amount Setting The surround (Karaoke mode) delay amount can be varied by setting the coefficient Tdos (12 bits from D14 to D3) value. However, the following restrictions apply according to the delay RAM assignment. Karaoke mode 0: Tdis + Tdos 7FF8H Karaoke mode 1 (1/2 decimation): Tdis + Tdos 7FF8H Karaoke mode 1 (1/3 decimation): Tdis + Tdos 7FF0H The relationships between the coefficient and the delay amount are shown in Table 7-2-8. Coefficients TpL1 to 3 (12 bits from D14 to D3) and TpR1 to 3 (12 bits from D14 to D3) are the sound initial delay time. Set in the range of 0008H to Tdos. Setting value Tdos Karaoke mode 0 0008H 0010H 0018H * 2FF8H * * 7FE8H 7FF0H Karaoke mode 1 Karaoke mode 0 Delay (fs = 44.1kHz) 1/2 decimation 1/3 decimation
1535 steps 4094 steps 1/fs per step setting possible 2/fs per step setting possible 3/fs per step setting possible 0.022ms 0.045ms 0.068ms * * * * * * * * * 34.807ms * * * * * * * * 185.667ms 278.503ms Table 7-2-8. Surround Karaoke Mode Delay Amount Setting
- 36 -
CXD2721Q-1
7-2-5. I/O Level Settings [Relevant coefficients] Ki (address = 00H), KisLm (address = 08H), KisRc (address = 09H), KiaLm (address = 0AH), KiaRc (address = 0BH), KisRm (address = 0CH), KisLc (address = 0DH), KiaRm (address = 0EH), KiaLc (address = 0FH), Kimc (address = 3BH), Krmd (address = 53H), Krme (address = 54H), Krmpd (address = 55H), Krmpe (address = 56H), Kdryd (address = 59H), Keffd (address = 5AH), KLmd (address = 5CH), KRmd (address = 5DH), KLsd (address = 5EH), KRsd (address = 5FH), KLod (address = 60H), KRod (address = 61H), Kdrys (address = 62H), Keffs (address = 63H), KLms (address = 65H), KRms (address = 66H), KLss (address = 67H), KRss (address = 68H), KLos (address = 69H), KRos (address = 6AH), Kre (address = 6FH), Krd (address = 73H), Kfb (address = 74H), KLri (address = 81H), KRri (address = 82H), Kfbs (address = 83H), KLtp1 (address = 85H), KLtp2 (address = 86H), KLtp3 (address = 87H), KRtp1 (address = 88H), KRtp2 (address = 89H), KRtp3 (address = 8AH) The I/O levels and volumes are 2's complement format with the decimal point between D15 and D14, and hexadecimal notation with D15 as MSB and D0 as LSB. The coefficient and level relationships are as follows. D15 to D0 8000H FFFFH 0000H Level 0dB -90.31dB - D15 to D0 8000H FFFFH 0000H Level +12.04dB -78.27dB -
Table 7-2-9. I/O Level Settings (other than Kre)
Table 7-2-10. I/O Level Settings (Kre)
The I/O levels for 8001H to FFFEH are determined by the following formulas. (Coefficient value) = [(-1) x D15 + Dn x 2n-15] x (-1) for other than Kre
n=0 14
(Coefficient value) = [(-1) x D15 + Dn x 2n-15] x (-4) for Kre
n=0
14
I/O level = 20 log [coefficient value] dB As an exception to the above I/O levels, the surround output level for Karaoke mode 1 with a decimation ratio of 1/2 is shown in Table 7-2-11. D15 to D0 8000H FFFFH 0000H Level +6.02dB -84.29dB -
Table 7-2-11. I/O Level Settings (exception) Note) D15 to D0 are negative values, but the calculation is (-1) x (D15 to D0). When you wish to invert the phase, make D15 to D0 positive values. - 37 -
CXD2721Q-1
7-3. Music Mode 7-3-1. Fixed Values for System Initialization When the system is initialized, the coefficient RAM must be set to the fixed values shown below for internal operation. Address 01H 02H 03H 10H 11H 14H 20H 55H Fixed value 68A9H 5121H 0000H 8000H 82EAH 8000H 7FF7H 0000H Table 7-3-1. Note) Consult your Sony representative with regard to use at other than fs = 44.1kHz, as the fixed values change. 7-3-2. Setting Data The relationships between the coefficient RAM and each function during DSP operation are as follows. Address Symbol 00H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 15H 16H Ki Ke DC1a1 DC1a0 DC1b KisLm KisRc KiaLm KiaRc KisRm KisLc LiaRm KiaLc KLri KRri Function SI data input level control De-emphasis ON/OFF DC cut1 coefficient DC cut1 coefficient DC cut1 coefficient SI CH1 data Lch mix SI CH2 data Lch mix ADC CH1 data Lch mix ADC CH2 data Lch mix SI CH2 data Rch mix SI CH1 data Rch mix ADC CH2 data Rch mix ADC CH1 data Rch mix Surround input level control (Lch) Surround input level control (Rch) Setting value See Table 7-3-5 (1) ON/ac19H OFF/0000H See Table 9-1 See Table 9-1 See Table 9-1 See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1)
Table 7-3-2 (1). Coefficient RAM Setting Data (1/4) Note) See "8. DSP Signal Flow" regarding the symbols. - 38 -
CXD2721Q-1
Address Symbol 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 38H 39H 3AH 3BH k XthP XthM Ksd Kse Kdry KLeff KReff Kst Ap Am Bp Bm Cp Cm Khr a0/4 a1/4 a2 b1/4 b2 a0/4 a1/4 a2 b1/4 b2 a0/4 a1/4 a2 b1/4 b2 HDmp0 HDmp1 KLe0 KLe1
Function Compressor coefficient Compressor coefficient Compressor coefficient Compressor ON/OFF PEQ ON/OFF Direct sound mix Surround output (Lch) mix Surround output (Rch) mix Tone control ON/OFF Compressor coefficient Compressor coefficient Compressor coefficient Compressor coefficient Compressor coefficient Compressor coefficient PEQ input level control PEQ1 coefficient PEQ1 coefficient PEQ1 coefficient PEQ1 coefficient PEQ1 coefficient PEQ2 coefficient PEQ2 coefficient PEQ2 coefficient PEQ2 coefficient PEQ2 coefficient PEQ3 coefficient PEQ3 coefficient PEQ3 coefficient PEQ3 coefficient PEQ3 coefficient Surround hi-dump0 coefficient Surround hi-dump1 coefficient Surround Lch E/R tap0 volume Surround Lch E/R tap1 volume
Setting value See Table 7-3-3 See Table 7-3-3 See Table 7-3-3 ON/8000H OFF/0000H ON/8000H OFF/0000H See Table 7-3-5 (1) See Table 7-3-5 (1) See Table 7-3-5 (1) ON/8000H OFF/0000H See Table 7-3-3 See Table 7-3-3 See Table 7-3-3 See Table 7-3-3 See Table 7-3-3 See Table 7-3-3 See Table 7-3-5 (1) See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-7 See Table 9-6 See Table 9-6 See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2)
Table 7-3-2 (2). Coefficient RAM Setting Data (2/4) Note) See "8. DSP Signal Flow" regarding the symbols. - 39 -
CXD2721Q-1
Address Symbol 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH KRe0 KRe1 Kfb KLtp0 KLtp1 KLtp2 KLtp3 KLtp4 KLtp5 KLtp6 KLtp7 bL0 bL1 KLod KRod KRtp0 KRtp1 KRtp2 KRtp3 KRtp4 KRtp5 KRtp6 KRtp7 bR0 bR1 LER0 LER1 RER0 RER1 TdoER TdiSR Ltp0 Ltp1 Ltp2 Ltp3
Function Surround Rch E/R tap0 volume Surround Rch E/R tap1 volume Surround reverberation sound mix Surround Lch S/R tap0 volume Surround Lch S/R tap1 volume Surround Lch S/R tap2 volume Surround Lch S/R tap3 volume Surround Lch S/R tap4 volume Surround Lch S/R tap5 volume Surround Lch S/R tap6 volume Surround Lch S/R tap7 volume Surround Lch all pass F. coefficient Surround Lch all pass F. coefficient System volume (DAC) Lch System volume (DAC) Rch Surround Rch S/R tap0 volume Surround Rch S/R tap1 volume Surround Rch S/R tap2 volume Surround Rch S/R tap3 volume Surround Rch S/R tap4 volume Surround Rch S/R tap5 volume Surround Rch S/R tap6 volume Surround Rch S/R tap7 volume Surround Rch all pass F. coefficient Surround Rch all pass F. coefficient Surround Lch E/R read tap0 address Surround Lch E/R read tap1 address Surround Rch E/R read tap0 address Surround Rch E/R read tap1 address Surround E/R delay amount Surround S/R write address Surround Lch S/R read tap0 address Surround Lch S/R read tap1 address Surround Lch S/R read tap2 address Surround Lch S/R read tap3 address
Setting value See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Table 7-3-5 (2) See Table 7-3-5 (2) See Table 7-3-5 (1) See Table 7-3-5 (1) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Tables 7-3-5 (1) and (2) See Table 7-3-5 (2) See Table 7-3-5 (2) See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4
Table 7-3-2 (3). Coefficient RAM Setting Data (3/4) Note) See "8. DSP Signal Flow" regarding the symbols. - 40 -
CXD2721Q-1
Address Symbol 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Ltp4 Ltp5 Ltp6 Ltp7 Lap0i Lap0o Lap1i Lap1o Rtp0 Rtp1 Rtp2 Rtp3 Rtp4 Rtp5 Rtp6 Rtp7 Rap0i Rap0o Rap1i Rap1o TdoSR Kdsh bLB gLB bLT gLT bRB gRB bRT gRT KLos KRos
Function Surround Lch S/R read tap4 address Surround Lch S/R read tap5 address Surround Lch S/R read tap6 address Surround Lch S/R read tap7 address Surround Lch all pass F.0 write Surround Lch all pass F.0 read Surround Lch all pass F.1 write Surround Lch all pass F.1 read Surround Rch S/R read tap0 address Surround Rch S/R read tap1 address Surround Rch S/R read tap2 address Surround Rch S/R read tap3 address Surround Rch S/R read tap4 address Surround Rch S/R read tap5 address Surround Rch S/R read tap6 address Surround Rch S/R read tap7 address Surround Rch all pass F.0 write Surround Rch all pass F.0 read Surround Rch all pass F.1 write Surround Rch all pass F.1 read Surround S/R delay amount Tone control input level control Tone control (bass) Lch coefficient Tone control (bass) Lch gain Tone control (treble) Lch coefficient Tone control (treble) Lch gain Tone control (bass) Rch coefficient Tone control (bass) Rch gain Tone control (treble) Rch coefficient Tone control (treble) Rch gain System volume (SO) Lch System volume (SO) Rch
Setting value See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-4 See Table 7-3-5 (1) See Table 9-8 See Table 9-8 See Table 9-9 See Table 9-9 See Table 9-8 See Table 9-8 See Table 9-9 See Table 9-9 See Table 7-3-5 (1) See Table 7-3-5 (1)
Table 7-3-2 (4). Coefficient RAM Setting Data (4/4) Note) See "8. DSP Signal Flow" regarding the symbols.
- 41 -
CXD2721Q-1
7-3-3. Compressor [Relevant coefficients] k (address = 17H), Xthp (address = 18H), XthM (address = 19H), Ksd (address = 1AH), Ap (address = 21H), Am (address = 22H), Bp (address = 23H), Bm (address = 24H), Cp (address = 25H), Cm (address = 26H) The parameter table is shown in Table 7-3-3. The I/O characteristics for the various parameters in the table are as shown in Fig. 7-3-3. threshold XthM Comp 5 XthP gain k 6.0 [dB] 2.0 4000 5.2 [dB] 20/11 3A2E 4.4 [dB] 5/3 3555 2.9 [dB] 7/5 2CCC 1.6 [dB] 6/5 2666 -9/20 F19A 9/20 0E66 3/2 3000 3/2 3000 -1/20 F99A 1/99 0666 -5/8 EC00 5/8 1400 33/20 34CC 33/20 34CC -1/40 FCCD 1/40 0333 -49/54 E2F7 49/54 1D09 52/27 3DA1 52/27 3DA1 -1/54 FDA2 1/54 025E -100/99 DFAE 100/99 2052 200/99 40A5 200/99 40A5 -1/99 FEB6 1/99 014A -1.0 E000 1.0 2000 2.0 4000 2.0 4000 0 0000 0 0000 Ap Am coefficient Bp Bm Cp Cm
-20 [dB] 0 0000 0 0000
-20 [dB] Comp 4 -1/10 F334 1/10 0CCC
-17 [dB] Comp 3 -1/7 EDB7 1/7 1249
-14 [dB] Comp 2 -1/5 E667 1/5 1999
-9.5 [dB] Comp 1 -1/3 D556 1/3 2AAA
Table 7-3-3. Compressor Parameter Table
- 42 -
CXD2721Q-1
Input Level [dB]
-30 0 -20 -10
Comp 5 -10 Comp 4 Comp 3 Comp 2 Comp 1 6.0 [dB] -20 Linear
Output Level [dB]
-30
-20 Comp 4
-1 -14 Comp 3 Comp 2 Threshold Level [dB]
-9.5 Comp 1
Fig. 7-3-3. Compressor I/O Characteristics
- 43 -
CXD2721Q-1
7-3-4. Surround [Relevant coefficients] kLri (address = 15H), KRri (address = 16H), HDmp0 (address = 38H), HDmp1 (address = 39H), KLe0 (address = 3AH), KLe1 (address = 3BH), KRe0 (address = 3CH), KRe1 (address = 3DH), Kfb (address = 3EH), KLtp0 (address = 3FH), KLtp1 (address = 40H), KLtp2 (address = 41H), KLtp3 (address = 42H), KLtp4 (address = 43H), KLtp5 (address = 44H), KLtp6 (address = 45H), KLtp7 (address = 46H), bL0 (address = 47H), bL1 (address = 48H), KRtp0 (address = 4BH), KRtp1 (address = 4CH), KRtp2 (address = 4DH), KRtp3 (address = 4EH), KRtp4 (address = 4FH), KRtp5 (address = 50H), KRtp6 (address = 51H), KRtp7 (address = 52H), bR0 (address = 53H), bR1 (address = 54H), TdiER (address = 55H), LER0 (address = 56H), LER1 (address = 57H), RER0 (address = 58H), RER1 (address = 59H), TdoES (address = 5AH), TdiSR (address = 5BH), Ltp0 (address = 5CH), Ltp1 (address = 5DH), Ltp2 (address = 5EH), Ltp3 (address = 5FH), Ltp4 (address = 60H), Ltp5 (address = 61H), Ltp6 (address = 62H), Ltp7 (address = 63H), Lap0i (address = 64H), Lap0o (address = 65H), Lap1i (address = 66H), Lap1o (address = 67H), Rtp0 (address = 68H), Rtp1 (address = 69H), Rtp2 (address = 6AH), Rtp3 (address = 6BH), Rtp4 (address = 6CH), Rtp5 (address = 6DH), Rtp6 (address = 6EH), Rtp7 (address = 6FH), Rap0i (address = 70H), Rap0o (address = 71H), Rap1i (address = 72H), Rap1o (address = 73H), TdoSR (address = 74H) * Delay amount setting The built-in delay RAM capacity which can be used in music mode is 128K bits (approximately 185ms). The surround block has a number of delay lines for initial reverberation sound and higher-order reverberation sound, and the delay RAM can be assigned freely to these delay lines. However, the following restrictions apply. 0000H TdoES FFD0H Determines the initial reverberation sound delay amount TdoES TdiSR FFD0H TdiSR + TdoSR FFD0H Determines the higher-order reverberation sound delay amount TdiSR + Lap0i FFD8H (Lap0i TdoSR + 0008H) TdiSR + Lap0o FFE0H (Lap0o 0008H) TdiSR + Lap1i FFE0H (Lap1i Lap0o) TdiSR + Lap1o FFE8H (Lap1o 0008H) TdiSR + Rap0i FFE8H (Rap0i Lap1o) TdiSR + Rap0o FFF0H (Rap0o 0008H) TdiSR + Rap1i FFF0H (Rap1i Rap0o) TdiSR + Rap1o FFF8H (Rap1o 0008H) (LER0, LER1, RER0, RER1) TdoER (Ltp, Rtp) TdoSR As shown above, the delay amount can be set to "0" for all delay lines other than the all-pass filter for through operation. Fig. 7-3-4 shows the setting example where the delay RAM is used to the fullest extent. Also, the relationships between the delay amount and coefficients are shown in Table 7-3-4. - 44 -
CXD2721Q-1
Setting values TdoER, TdoSR 0000H 0008H 0010H * * * FFF0H FFF8H
Delay (Fs = 44.1kHz) 1Fs [ms] setting possible 0.023ms 0.045ms 0.068ms * * * 185.71ms 185.73ms
Table 7-3-4. Music Mode Delay Amount Setting
TdoER = TdiSR 0000H 3200H
TdoSR 6E30H
Lap0i 6E38H
Lap0o = Lap1i 8A58H
Lap1o = Rap0i 9D48H
Rap0o = Rap1i BA68H
Rap1o CDF8H
TdiSR + Rap1o = 3200H + CDF8H = FFF8H Approximately 185ms (0000H to FFF8H)
Fig. 7-3-4. Music Mode Delay RAM Setting Example
- 45 -
CXD2721Q-1
7-3-5. I/O Level Settings [Relevant coefficients] (1) Ki (address = 00H), KisLm (address = 08H), KisRc (address = 09H), KiaLm (address = 0AH), KiaRc (address = 0BH), KisRm (address = 0CH), KisLc (address = 0DH), KiaRm (address = 0EH), KiaLc (address = 0FH), KLri (address = 15H), KRri (address = 16H), Kdry (address = 1CH), KLeff (address = 1DH), KReff (address = 1EH), Khr (address = 27H), KLe0 (address = 3AH), KLe1 (address = 3BH), KRe0 (address = 3CH), KRe1 (address = 3DH), KLod (address = 49H), KRod (address = 4AH), Kdsh (address = 75H), KLos (address = 7EH), KRos (address = 7FH) (2) Kfb (address = 3EH), KLtp0 (address = 3FH), KLtp1 (address = 40H), KLtp2 (address = 41H), KLtp3 (address = 42H), KLtp4 (address = 43H), KLtp5 (address = 44H), KLtp6 (address = 45H), KLtp7 (address = 46H), bL0 (address = 47H), bL1 (address = 48H), KRtp0 (address = 4BH), KRtp1 (address = 4CH), KRtp2 (address = 4DH), KRtp3 (address = 4EH), KRtp4 (address = 4FH), KRtp5 (address = 50H), KRtp6 (address = 51H), KRtp7 (address = 52H), bR0 (address = 53H), bR1 (address = 54H) The I/O levels and volumes are 2's complement format with the decimal point between D15 and D14, and hexadecimal notation with D15 as MSB and D0 as LSB. The coefficient and level relationships differ for the relevant coefficients (1) and (2) above, with negative values specified for (1) and positive values for (2). These cases are shown in Tables 7-3-5 (1) and (2), respectively. Also, phase inverted output is possible for relevant coefficients above which are marked with an asterisk () by reversing the positive/negative specification. D15 to D0 8000H FFFFH 0000H Level 0dB -90.31dB - D15 to D0 7FFFH 0001H 0000H Level Approximately 0dB -90.31dB -
Table 7-3-5 (1). I/O Level Settings (negative values)
Table 7-3-5 (2). I/O Level Settings (positive values)
The I/O levels for 8000H to FFFFH are determined by the following formulas. (Coefficient value) = [(-1) x D15 + Dn x 2n-15] x (-1)
n=0 14
I/O level = 20 log [coefficient value] dB Note) D15 to D0 are negative values, but the calculation is (-1) x (D15 to D0). The I/O levels for 7FFFH to 0001H are determined by the following formulas. (Coefficient value) = [D15 + Dn x 2n-15]
n=0 14
I/O level = 20 log [coefficient value] dB
- 46 -
8. DSP Signal Flow
8-1. Karaoke Mode Overall
53H -Krmd 62H -Kdrys 65H -KLms -KLos 69H 67H -KLss 54H -Krmpd Pitch Control 66H -KRms 56H -Krmpe 63H -Keffs -Kfb 74H Delay Line High Cut2 75 to 77H -Kre Over Sampling 08H -KisLm 09H -KisRc 0AH -KiaLm 0BH -KiaRc 19H 0DH -KisLc 11 to 12H 0CH -KisRm 0FH -KiaLc 0EH -KiaRm Pitch Control Voice Cancel 1BH 22 to 2EH Pitch Control Li Lo Surround Ri Ro See 8-2. 5FH -KRsd 5DH -KRmd 5AH -Keffd -KRod 61H DA2 Over Sampling DAC 59H -Kdryd 5CH -KLmd 5EH -KLsd -KLod 60H 6FH Tre 71H 6EH Tdoe 6AH -KRos 1EH 47H 68H -KRss SO2 PEQ 44 to 46H -Krme 55H High Cut1 SO1
-Kimc
MIC
ADC
Decimation
DC Cut2
3D to 3FH 3BH 40 to 43H
-Krd Down Sampling 73H
- 47 -
-Ki
SI1
04H DeEmphasis
00H -Ki
SI2
DeEmphasis DA1 Over Sampling DAC
AD1
ADC
Decimation
DC Cut1
AD2
ADC
Decimation
DC Cut1
05 to 07H
CXD2721Q-1
CXD2721Q-1
8-2. Karaoke Mode Surround
Lo -KLtp1 -KLri Li 81H Hi Dump -KRri Ri 82H 88H -KRtp1 89H 2 8AH 3 Ro 84H 83H 8DH 8EH 8FH 90H TpL1 TpL2 TpL3 Tdis Delay Line Tdos 94H -Kfbs 85H 2 86H 3 87H
TpR1 TpR2 TpR3 91H 92H 93H
- 48 -
8-3. Music Mode Overall
-Ki 00H -KisRc -KiaLm -KiaRc 08 to 0FH -KisRm -KisLc -KiaRm -KiaLc
-KisLm
SI1
DeEmphasis
-Ki
SI2
DeEmphasis
AD1
ADC
Decimation
DC Cut1
AD2
ADC
Decimation
DC Cut1
05 to 07H
- 49 -
1FH, 75 to 79H SO1 -KLos 7EH 1FH, 75H, 7A to 7DH -KLod 49H Over Sampling DAC -Kdry 15, 16H, 38 to 48H, 1CH Bass/Treble Torn Control 4B to 74H Surround Block -KLeff 1DH -KReff 1EH -Kdry 1CH PEQ DA1 1FH, 75H, 7A to 7DH SO2 Bass/Treble Torn Control -KRos 7FH -KRod Over Sampling 4AH DAC PEQ DA2 CXD2721Q-1
17 to 1AH, 21 to 26H 1BH, 27 to 36H
Compressor
Compressor
8-4. Music Mode Surround
EARLY REFFLECTIONS bL0 47H bL1 48H
64H
65H
66H
67H x4 Lch out -bL1
-KLe0 -bL0 KLtp0 3f to 46H Kfb 3EH 5CH 5DH 5EH 5FH 60H 61H 62H 63H HI_Dump 1 5BH 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 74H 39H 1 2 3 4 5 6 7
-KLe1
3AH
3BH
ALLPASS FILTER
-KLri
Lch in
15H
56H 57H
- 50 -
KRtp0 -KRe1 3DH 1 2 3 4 5 6 7 3B to 52H 70H
HI_Dump 0
5AH
38H
58H 59H
16H
Rch in
-KRri
-KRe0
3CH
bR0 53H
bR1 54H x4 71H 72H 73H Rch out
-bR0
-bR1
CXD2721Q-1
CXD2721Q-1
9. Filter Coefficient Tables The cut-off frequencies and PEQ gain, Q, and center frequency settings for each signal flow filter are shown in Tables 9-1 to 9-9. Note that if the above setting values are changed during DSP operation, the output level becomes unstable for several 1/fs. Tables 9-1 to 9-5 and digital de-emphasis are given for fs = 44.1kHz. Consult your Sony representative with regard to use at other than this value. (1) DC Cut1 for Karaoke Mode or Music Mode Accompaniment/DC Cut2 for Karaoke Mode Voice [Relevant coefficients] DC1a1 (address = 05H), DC1a0 (address = 06H), DC1b (address = 07H), DC2a1 (address = 3DH), DC2a0 (address = 3EH), DC2b (address = 3FH) Cut-off frequency [Hz] 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 DC1a1 DC2a1 7FD1 7FBA 7FA2 7F8B 7F74 7F5D 7F46 7F2F 7F18 7F01 7EEA 7ED3 7EBC 7EA5 7E8E 7E77 7E61 7E4A 7E33 7E1C 7E06 7DEF 7DD9 7DC2 7DAC DC1a0 DC2a0 802F 8046 805E 8075 808C 80A3 80BA 80D1 80E8 80FF 8116 812D 8144 815B 8172 8189 819F 81B6 81CD 81E4 81FA 8211 8227 823E 8254 DC1b DC2b 7FA2 7F74 7F45 7F17 7EE9 7EBA 7E8C 7E5E 7E30 7E02 7DD4 7DA6 7D78 7D4B 7D1D 7CEF 7CC2 7C94 7C67 7C39 7C0C 7BDF 7BB2 7B85 7B58 Table 9-1. Cut-off frequency [Hz] 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 OFF DC1a1 DC2a1 7D95 7D7F 7D68 7D52 7D3B 7D25 7D0F 7CF8 7CE2 7CCC 7CB6 7CA0 7C8A 7C73 7C5D 7C47 7C31 7C1B 7C05 7BEF 7BDA 7BC4 7BAE 7B98 0000 DC1a0 DC2a0 826B 8281 8298 82AE 82C5 82DB 82F1 8308 831E 8334 834A 8360 8376 838D 83A3 83B9 83CF 83E5 83FB 8411 8426 843C 8452 8468 8000 DC1b DC2b 7B2B 7AFE 7AD1 7AA4 7A77 7A4B 7A1E 79F1 79C5 7998 796C 7940 7914 78E7 78BB 788F 7863 7837 780B 77DF 77B4 7788 775C 7731 0000
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CXD2721Q-1
(2) High Cut1 for Karaoke Mode Voice [Relevant coefficients] HC1a1 (address = 44H), HC1a0 (address = 45H), HC1b (address = 46H) Cut-off frequency [Hz] 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5300 5400 5500 HC1b 6EF2 6D5C 6BCB 6A3E 68B6 6733 65B4 6439 62C3 6150 5FE2 5E77 5D11 5BAE 5A4E 58F2 579A 5645 54F3 53A4 5259 5110 4FCB 4E88 4D48 4C0B 4AD0 4998 4863 4730 4600 44D2 43A6 427C 4155 4030 3F0D 3DEC 3CCD 3BAF 3A94 397B 3863 374D 3639 3527 HC1a1 0886 0951 0A1A 0AE0 0BA4 0C66 0D25 0DE3 0E9E 0F57 100E 10C4 1177 1228 12D8 1386 1432 14DD 1586 162D 16D3 1777 181A 18BB 195B 19FA 1A97 1B33 1BCE 1C67 1CFF 1D96 1E2C 1EC1 1F55 1FE7 2079 2109 2199 2228 22B5 2342 23CE 2459 24E3 256C HC1a0 F77A F6AF F5E6 F520 F45C F39A F2DB F21D F162 F0A9 EFF2 EF3C EE89 EDD8 ED28 EC7A EBCE EB23 EA7A E9D3 E92D E889 E7E6 E745 E6A5 E606 E569 E4CD E432 E399 E301 E26A E1D4 E13F E0AB E019 DF87 DEF7 DE67 DDD8 DD4B DCBE DC32 DBA7 DB1D DA94 Table 9-2. Cut-off frequency [Hz] 5600 5700 5800 5900 6000 6100 6200 6300 6400 6500 6600 6700 6800 6900 7000 7100 7200 7300 7400 7500 7600 7700 7800 7900 8000 8100 8200 8300 8400 8500 8600 8700 8800 8900 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000 OFF HC1b 3416 3306 31F9 30EC 2FE2 2ED8 2DD0 2CCA 2BC4 2AC0 29BD 28BC 27BB 26BC 25BD 24C0 23C4 22C9 21CF 20D5 1FDD 1EE6 1DEF 1CF9 1C04 1B10 1A1C 192A 1838 1746 1655 1565 1475 1386 1298 11A9 10BC 0FCF 0EE2 0DF5 0D09 0C1E 0B32 0A47 095C 0000 HC1a1 25F4 267C 2703 2789 280E 2893 2917 299A 2A1D 2A9F 2B21 2BA1 2C22 2CA1 2D21 2D9F 2E1D 2E9B 2F18 2F95 3011 308C 3108 3183 31FD 3277 32F1 336A 33E3 345C 34D5 354D 35C5 363C 36B3 372B 37A1 3818 388E 3905 397B 39F0 3A66 3ADC 3B51 0000 HC1a0 DA0C D984 D8FD D877 D7F2 D76D D6E9 D666 D5E3 D561 D4DF D45F D3DE D35F D2DF D261 D1E3 D165 D0E8 D06B CFEF CF74 CEF8 CE7D CE03 CD89 CD0F CC96 CC1D CBA4 CB2B CAB3 CA3B C9C4 C94D C8D5 C85F C7E8 C772 C6FB C685 C610 C59A C524 C4AF 8000
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CXD2721Q-1
(3) High Cut2 for Microphone Echo [Relevant coefficients] HC2a1 (address = 75H), HC2a0 (address = 76H), HC2b (address = 77H) Conditions: Microphone echo decimation ratio 1/2 Cut-off frequency [Hz] 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5300 5400 5500 HC2b 5FE2 5D11 5A4E 579A 54F3 5259 4FCB 4D48 4AD0 4863 4600 43A6 4155 3F0D 3CCD 3A94 3863 3639 3416 31F9 2FE2 2DD0 2BC4 29BD 27BB 25BD 23C4 21CF 1FDD 1DEF 1C04 1A1C 1838 1655 1475 1298 10BC 0EE2 0D09 0B32 095C 0788 05B3 03E0 020D 003A HC2a1 100E 1177 12D8 1432 1586 16D3 181A 195B 1A97 1BCE 1CFF 1E2C 1F55 2079 2199 22B5 23CE 24E3 25F4 2703 280E 2917 2A1D 2B21 2C22 2D21 2E1D 2F18 3011 3108 31FD 32F1 33E3 34D5 35C5 36B3 37A1 388E 397B 3A66 3B51 3C3B 3D26 3E0F 3EF9 3FE2 HC2a0 EFF2 EE89 ED28 EBCE EA7A E92D E7E6 E6A5 E569 E432 E301 E1D4 E0AB DF87 DE67 DD4B DC32 DB1D DA0C D8FD D7F2 D6E9 D5E3 D4DF D3DE D2DF D1E3 D0E8 CFEF CEF8 CE03 CD0F CC1D CB2B CA3B C94D C85F C772 C685 C59A C4AF C3C5 C2DA C1F1 C107 C01E Cut-off frequency [Hz] 5600 5700 5800 5900 6000 6100 6200 6300 6400 6500 6600 6700 6800 6900 7000 7100 7200 7300 7400 7500 7600 7700 7800 7900 8000 8100 8200 8300 8400 8500 8600 8700 8800 8900 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 10000 OFF HC2b FE68 FC95 FAC2 F8EE F719 F543 F36C F194 EFBB EDE0 EC02 EA23 E841 E65D E476 E28C E09F DEAE DCBA DAC1 D8C5 D6C4 D4BE D2B3 D0A3 CE8E CC72 CA50 C828 C5F9 C3C2 C184 BF3E BCEF BA98 B837 B5CC B357 B0D7 AE4C ABB5 A911 A660 A3A1 A0D4 0000 HC2a1 40CC 41B5 429F 4389 4473 455E 464A 4736 4822 4910 49FF 4AEE 4BDF 4CD1 4DC5 4EBA 4FB0 50A9 51A3 529F 539D 549E 55A1 56A6 57AE 58B9 59C7 5AD8 5BEC 5D03 5E1F 5F3E 6061 6188 62B4 63E4 651A 6654 6794 68DA 6A25 6B77 6CD0 6E2F 6F96 0000 HC2a0 BF34 BE4B BD61 BC77 BB8D BAA2 B9B6 B8CA B7DE B6F0 B601 B512 B421 B32F B23B B146 B050 AF57 AE5D AD61 AC63 AB62 AA5F A95A A852 A747 A639 A528 A414 A2FD A1E1 A0C2 9F9F 9E78 9D4C 9C1C 9AE6 99AC 986C 9726 95DB 9489 9330 91D1 906A 8000
Table 9-3 (1).
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CXD2721Q-1
Conditions: Microphone echo decimation ratio 1/3 Cut-off frequency [Hz] 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 HC1b 5259 4E88 4AD0 4730 43A6 4030 3CCD 397B 3639 3306 2FE2 2CCA 29BD 26BC 23C4 20D5 1DEF 1B10 1838 1565 1298 0FCF 0D09 0A47 0788 04CA HC1a1 16D3 18BB 1A97 1C67 1E2C 1FE7 2199 2342 24E3 267C 280E 299A 2B21 2CA1 2E1D 2F95 3108 3277 33E3 354D 36B3 3818 397B 3ADC 3C3B 3D9A HC1a0 E92D E745 E569 E399 E1D4 E019 DE67 DCBE DB1D D984 D7F2 D666 D4DF D35F D1E3 D06B CEF8 CD89 CC1D CAB3 C94D C7E8 C685 C524 C3C5 C266 Cut-off frequency [Hz] 3600 3700 3800 3900 4000 4100 4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 OFF HC1b 020D FF51 FC95 F9D8 F719 F458 F194 EECD EC02 E932 E65D E381 E09F DDB4 DAC1 D7C5 D4BE D1AC CE8E CB62 C828 C4DE C184 BE18 BA98 0000 HC1a1 3EF9 4057 41B5 4314 4473 45D4 4736 4899 49FF 4B67 4CD1 4E3F 4FB0 5126 529F 541D 55A1 572A 58B9 5A4F 5BEC 5D91 5F3E 60F4 62B4 0000 HC1a0 C107 BFA9 BE4B BCEC BB8D BA2C B8CA B767 B601 B499 B32F B1C1 B050 AEDA AD61 ABE3 AA5F A8D6 A747 A5B1 A414 A26F A0C2 9F0C 9D4C 8000
Table 9-3 (2).
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CXD2721Q-1
(4) PEQ for Voice [Relevant coefficients] PEQa (address = 40H), PEQb1 (address = 41H), PEQb2 (address = 42H), PEQg (address = 43H) Center frequency [Hz] 250.0 280.6 315.0 353.6 396.9 445.4 500.0 561.2 630.0 707.1 793.7 890.9 1000.0 1122.5 1259.9 1414.2 1587.4 1781.8 2000.0 2244.9 2519.8 2828.4 3174.8 3563.6 4000.0 4489.8 5039.7 5656.9 6349.6 7127.2 8000.0 PEQa 023D 0282 02CF 0325 0385 03F0 0467 04EC 0580 0624 06DB 07A6 0886 097E 0A91 0BC0 0D0D 0E7C 100E 11C7 13A8 15B5 17F1 1A5E 1CFF 1FD8 22ED 2642 29DB 2DC1 31FD Table 9-4. PEQb1 7DAE 7D64 7D10 7CB2 7C47 7BCF 7B48 7AAE 7A01 793D 785E 7762 7643 74FD 738B 71E5 7004 6DE0 6B6D 68A1 656E 61C6 5D97 58CF 535A 4D24 4617 3E23 353B 2B5C 2097 PEQb2 847B 8505 859F 864B 870B 87E1 88CF 89D9 8B01 8C4A 8DB7 8F4D 910E 92FE 9524 9781 9A1C 9CFA A01E A38F A752 AB6C AFE4 B4BE BA00 BFB2 C5DC CC85 D3B8 DB84 E3FC Gain [dB] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 Table 9-5. PEQg 0000 01E5 03E7 0608 0849 0AAC 0D33 0FE1 12B7 15B8 18E7 1C46 1FD9 23A1 27A3 2BE2 3061 3524 3A30 3F88 4531 4B30 518A 5844 5F64
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CXD2721Q-1
(5) Hi-dump F. for Karaoke Mode/Music Mode [Relevant coefficients] HDmp (address = 84H): Karaoke mode HDmp0 (address = 38H), HDmp1 (address = 39H): Music mode Use 1/1 for music mode. fc [Hz] 40 60 80 100 200 400 600 800 -HDmp 1/1 FF46 FEEA FE8D FE31 FC68 F8EA F585 F23A 1/2 FE8D FDD5 FD1E FC68 F8EA F23A EBEE E603 1/3 FDD5 FCC3 FBB3 FAA6 F585 EBEE E32F DB3B Table 9-6. fc [Hz] 1k 2k 4k 6k 8k 10k 12k 14k -HDmp 1/1 EF08 E073 C97A B91E AD94 A578 9FC6 9BCC 1/2 E073 C97A AD94 9FC6 9912 1/3 D404 B91E 9FC6 974D
(6) PEQ for Music Mode [Relevant coefficients] Kse (address = 1BH), Khr (address = 27H), a0/4 (address = 28H, 2DH, 32H), a1/4 (address = 29H, 2EH, 33H), a2 (address = 2AH, 2FH, 34H), b1/4 (address = 2BH, 30H, 35H), b2 (address = 2CH, 31H, 36H) Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 a0/4 2037 2028 201C 2012 200B 2005 2000 1FFB 1FF5 1FEE 1FE4 1FD8 1FCA a1/4 C025 C025 C025 C025 C025 C025 C025 C02E C03A C049 C05C C074 C091 a2 7E92 7ECE 7EFE 7F24 7F42 7F5A 7F6D 7F5A 7F42 7F24 7EFF 7ECF 7E94 b1/4 3FDB 3FDB 3FDB 3FDB 3FDB 3FDB 3FDB 3FD2 3FC6 3FB7 3FA4 3F8C 3F6F b2 8093 8093 8093 8093 8093 8093 8093 80B9 80E9 8125 8170 81CF 8246
Table 9-7 (1). PEQ Parameter Table (f0 = 22.1 [Hz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 204E 2038 2027 201A 200F 2007 2000 1FF9 1FF1 1FE6 1FD9 1FC8 1FB3
a1/4 C034 C034 C034 C034 C034 C034 C034 C042 C052 C068 C082 C0A4 C0CD
a2 7DFA 7E4F 7E93 7EC8 7EF3 7F15 7F30 7F15 7EF4 7EC9 7E94 7E52 7DFF
b1/4 3FCC 3FCC 3FCC 3FCC 3FCC 3FCC 3FCC 3FBE 3FAE 3F98 3F7E 3F5C 3F33
b2 80D0 80D0 80D0 80D0 80D0 80D0 80D0 8106 8149 819E 8208 828E 8335
Table 9-7 (2). PEQ Parameter Table (f0 = 31.3 [Hz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 206D 204F 2037 2025 2015 2009 2000 1FF7 1FEB 1FDC 1FC9 1FB1 1F94
a1/4 C04A C04A C04A C04A C04A C04A C04A C05D C074 C092 C0B7 C0E6 C121
a2 7D25 7D9D 7DFD 7E48 7E85 7EB5 7EDB 7EB5 7E86 7E4A 7E00 7DA3 7D2F
b1/4 3FB6 3FB6 3FB6 3FB6 3FB6 3FB6 3FB6 3FA3 3F8C 3F6E 3F49 3F1A 3EDF
b2 8125 8125 8125 8125 8125 8125 8125 8171 81D0 8247 82DC 8397 8481
Table 9-7 (3). PEQ Parameter Table (f0 = 44.2 [Hz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 209A 2070 204E 2034 201E 200D 2000 1FF3 1FE2 1FCD 1FB2 1F92 1F69
a1/4 C068 C068 C068 C068 C068 C068 C068 C083 C0A4 C0CE C102 C144 C195
a2 7BF8 7CA2 7D29 7D94 7DE9 7E2C 7E62 7E2D 7DEB 7D98 7D30 7CAE 7C0B
b1/4 3F98 3F98 3F98 3F98 3F98 3F98 3F98 3F7D 3F5C 3F32 3EFE 3EBC 3E6B
b2 819E 819E 819E 819E 819E 819E 819E 8209 828E 8335 8407 850C 8652
Table 9-7 (4). PEQ Parameter Table (f0 = 62.5 [Hz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 20DA 209E 206E 2049 202B 2013 2000 1FED 1FD6 1FB8 1F93 1F65 1F2C
a1/4 C093 C093 C093 C093 C093 C093 C093 C0B9 C0E8 C122 C16B C1C6 C238
a2 7A51 7B40 7BFE 7C95 7D0D 7D6C 7DB8 7D6E 7D11 7C9D 7C0C 7B57 7A76
b1/4 3F6D 3F6D 3F6D 3F6D 3F6D 3F6D 3F6D 3F47 3F18 3EDE 3E95 3E3A 3DC8
b2 8248 8248 8248 8248 8248 8248 8248 82DE 8399 8484 85A8 8715 88DA
Table 9-7 (5). PEQ Parameter Table (f0 = 88.4 [Hz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 2133 20DE 209C 2066 203C 201B 2000 1FE5 1FC4 1F9B 1F67 1F27 1ED8
a1/4 C0D0 C0D0 C0D0 C0D0 C0D0 C0D0 C0D0 C105 C146 C198 C1FE C27C C318
a2 77FE 794F 7A5B 7B2F 7BD8 7C5E 7CC9 7C61 7BE0 7B3E 7A75 797C 7848
b1/4 3F30 3F30 3F30 3F30 3F30 3F30 3F30 3EFB 3EBA 3E68 3E02 3D84 3CE8
b2 8337 8337 8337 8337 8337 8337 8337 8409 850F 8656 87ED 89E6 8C57
Table 9-7 (6). PEQ Parameter Table (f0 = 125.0 [Hz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 21B0 2139 20DB 2090 2055 2025 2000 1FDB 1FAC 1F72 1F2B 1ED2 1E66
a1/4 C127 C127 C127 C127 C127 C127 C127 C170 C1CB C23D C2C9 C377 C44C
a2 74BB 7696 780E 7939 7A27 7AE4 7B7A 7AEA 7A36 7957 7843 76EE 754C
b1/4 3ED9 3ED9 3ED9 3ED9 3ED9 3ED9 3ED9 3E90 3E35 3DC3 3D37 3C89 3BB4
b2 8486 8486 8486 8486 8486 8486 8486 85AB 8719 88DF 8B12 8DC8 911C
Table 9-7 (7). PEQ Parameter Table (f0 = 176.8 [Hz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 225E 21B7 2133 20CA 2077 2035 2000 1FCC 1F8B 1F3B 1ED8 1E5F 1DCC
a1/4 C1A1 C1A1 C1A1 C1A1 C1A1 C1A1 C1A1 C206 C285 C321 C3E2 C4CD C5EC
a2 702F 72C9 74D9 767D 77CB 78D4 79A6 78E0 77E9 76B8 7541 7375 7146
b1/4 3E5F 3E5F 3E5F 3E5F 3E5F 3E5F 3E5F 3DFA 3D7B 3CDF 3C1E 3B33 3A14
b2 865A 865A 865A 865A 865A 865A 865A 87F2 89EC 8C5D 8F60 930F 978A
Table 9-7 (8). PEQ Parameter Table (f0 = 250.0 [Hz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 2350 2267 21AE 211B 20A6 204A 2000 1FB7 1F5D 1EEE 1E67 1DC4 1D00
a1/4 C24D C24D C24D C24D C24D C24D C24D C2DA C387 C45D C561 C69C C816
a2 69DD 6D80 7064 72B0 7483 75F6 771D 760D 74BE 7322 712C 6ECB 6BF0
b1/4 3DB3 3DB3 3DB3 3DB3 3DB3 3DB3 3DB3 3D26 3C79 3BA3 3A9F 3964 37EA
b2 88E3 88E3 88E3 88E3 88E3 88E3 88E3 8B17 8DCF 9125 9537 9A25 A011
Table 9-7 (9). PEQ Parameter Table (f0 = 353.6 [Hz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 249E 2359 2257 218A 20E8 2067 2000 1F9B 1F1F 1E88 1DD2 1CF8 1BF7
a1/4 C340 C340 C340 C340 C340 C340 C340 C401 C4EC C60B C764 C901 CAE9
a2 6127 6639 6A40 6D73 6FFE 7203 739D 722F 706F 6E4E 6BBC 68AA 650B
b1/4 3CC0 3CC0 3CC0 3CC0 3CC0 3CC0 3CC0 3BFF 3B14 39F5 389C 36FF 3517
b2 8C63 8C63 8C63 8C63 8C63 8C63 8C63 8F66 9317 9794 9CFE A375 AB18
Table 9-7 (10). PEQ Parameter Table (f0 = 500.0 [Hz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 2665 24A3 233E 2222 2141 208E 2000 1F74 1ECB 1E00 1D0E 1BF3 1AAC
a1/4 C498 C498 C498 C498 C498 C498 C498 C59B C6D5 C84F CA0F CC1D CE7C
a2 5544 5C4B 61DF 664E 69D3 6C9F 6ED8 6CF3 6AA9 67E9 64A5 60D0 5C62
b1/4 3B68 3B68 3B68 3B68 3B68 3B68 3B68 3A65 392B 37B1 35F1 33E3 3184
b2 9128 9128 9128 9128 9128 9128 9128 953B 9A2B A018 A722 AF64 B8EF
Table 9-7 (11). PEQ Parameter Table (f0 = 707.1 [Hz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 28C9 265F 2475 22EF 21B9 20C3 2000 1F41 1E5D 1D50 1C17 1AB0 191C
a1/4 C67B C67B C67B C67B C67B C67B C67B C7D2 C96C CB50 CD83 D008 D2DF
a2 454A 4EF1 569B 5CB2 6188 6560 686D 65FF 6317 5FA9 5BAA 5716 51EF
b1/4 3985 3985 3985 3985 3985 3985 3985 382E 3694 34B0 327D 2FF8 2D21
b2 9793 9793 9793 9793 9793 9793 9793 9CFD A374 AB16 B3FA BE2B C9A3
Table 9-7 (12). PEQ Parameter Table (f0 = 1.0 [kHz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 2BD4 2894 2600 23F3 2252 2107 2000 1F01 1DD6 1C7C 1AF3 193C 175D
a1/4 C90C C90C C90C C90C C90C C90C C90C CAC2 CCC3 CF15 D1B9 D4AA D7E0
a2 30F3 3DF2 4844 5077 56FA 5C27 6043 5D44 59C0 55B0 5110 4BE9 4648
b1/4 36F4 36F4 36F4 36F4 36F4 36F4 36F4 353E 333D 30EB 2E47 2B56 2820
b2 9FBD 9FBD 9FBD 9FBD 9FBD 9FBD 9FBD A6B7 AEE7 B860 C324 CF27 DC43
Table 9-7 (13). PEQ Parameter Table (f0 = 1.4 [kHz], Q = 0.7)
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CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 2FF4 2B92 2817 2553 2321 2163 2000 1EAC 1D26 1B6F 198B 1781 155B
a1/4 CCDA CCDA CCDA CCDA CCDA CCDA CCDA CEF9 D168 D426 D72C DA6F DDDE
a2 1563 26E9 34D5 3FE4 48AC 4FA6 5531 51A8 4D9A 490A 4400 3E92 38DA
b1/4 3326 3326 3326 3326 3326 3326 3326 3107 2E98 2BDA 28D4 2591 2222
b2 AACF AACF AACF AACF AACF AACF AACF B3A8 BDCD C93A D5D4 E36C F1BA
Table 9-7 (14). PEQ Parameter Table (f0 = 2.0 [kHz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 34B8 2F07 2A82 26EB 2411 21CD 2000 1E4C 1C65 1A50 1817 15C6 136C
a1/4 D1D6 D1D6 D1D6 D1D6 D1D6 D1D6 D1D6 D44B D70A DA0A DD3F E096 E3FA
a2 F586 0C49 1E5E 2CBB 3823 4133 4866 448B 403D 3B88 3680 3143 2BF2
b1/4 2E2A 2E2A 2E2A 2E2A 2E2A 2E2A 2E2A 2BB5 28F6 25F6 22C1 1F6A 1C06
b2 B79A B70A B70A B79A B79A B79A B79A C245 CE30 DB38 E924 F7A4 065C
Table 9-7 (15). PEQ Parameter Table (f0 = 2.8 [kHz], Q = 0.7)
- 63 -
CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 3A89 3340 2D75 28DC 2535 224E 2000 1DDA 1B86 1910 1687 13FB 117E
a1/4 D91B D91B D91B D91B D91B D91B D91B DBB8 DE8C E18A E49F E7B7 EABD
a2 CEA3 EBCB 02F3 1559 23F5 2F91 38C9 34F8 30D7 2C79 27F9 2375 1F0B
b1/4 26E5 26E5 26E5 26E5 26E5 26E5 26E5 2448 2174 1E76 1B61 1849 1543
b2 C737 C737 C737 C737 C737 C737 C737 D3A1 E113 EF48 FDEC 0C9E 1AFC
Table 9-7 (16). PEQ Parameter Table (f0 = 4.0 [kHz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 4091 379F 3084 2AE0 2664 22D4 2000 1D67 1AAC 17E2 151B 1269 0FDC
a1/4 E301 E301 E301 E301 E301 E301 E301 E55B E7D4 EA5B ECE0 EF51 F1A1
a2 A654 CA1C E688 FD1B 0F0A 1D49 289A 254D 21D8 1E4E 1AC7 175B 141F
b1/4 1CFF 1CFF 1CFF 1CFF 1CFF 1CFF 1CFF 1AA5 182C 15A5 1320 10AF 0E5F
b2 D766 D766 D766 D766 D766 D766 D766 E518 F377 0229 10CC 1F01 2C71
Table 9-7 (17). PEQ Parameter Table (f0 = 5.7 [kHz], Q = 0.7)
- 64 -
CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 458B 3B3B 330A 2C89 275E 2343 2000 1D0A 1A03 16FE 1410 114A 0EBA
a1/4 EFC9 EFC9 EFC9 EFC9 EFC9 EFC8 EFC9 F149 F2D2 F459 F5D6 F73D F88A
a2 8513 AE53 CF16 E91D FDC9 0E35 1B40 18BB 1626 1394 1115 0EB9 0C8A
b1/4 1037 1037 1037 1037 1037 1037 1037 0EB7 0D2E 0BA7 0A2A 08C3 0776
b2 E4C0 E4C0 E4C0 E4C0 E4C0 E4C0 E4C0 F31C 01CD 1072 1EAB 2C20 3890
Table 9-7 (18). PEQ Parameter Table (f0 = 8.0 [kHz], Q = 0.7)
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 47BB 3CD1 3426 2D44 27CC 2373 2000 1CE3 19BB 169F 13A3 10D6 0E47
a1/4 0176 0176 0176 0176 0176 0176 0176 0152 012D 0109 00E6 00C5 00A7
a2 7676 A21C C4C9 E053 F633 0794 1562 134D 1131 0F1E 0D1F 0B40 098A
b1/4 FE8A FE8A FE8A FE8A FE8A FE8A FE8A FEAE FED3 FEF7 FF1A FF3B FF59
b2 EA9E EA9E EA9E EA9E EA9E EA9E EA9E F929 07E1 1665 2456 3167 3D5C
Table 9-7 (19). PEQ Parameter Table (f0 = 11.3 [kHz], Q = 0.7)
- 65 -
CXD2721Q-1
Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12
a0/4 418A 3854 3103 2B33 2695 22EA 2000 1D54 1A8B 17B4 14E5 122E 0FA0
a1/4 1B03 1B03 1B03 1B03 1B03 1B03 1B03 18C2 1668 1403 11A3 0F59 0D30
a2 9FD5 C4AF E1F4 F934 0BAC 1A57 25FE 22D3 1F83 1C25 18CE 1595 128D
b1/4 E4FD E4FD E4FD E4FD E4FD E4FD E4FD E73E E998 EBFD EE5D F0A7 F2D0
b2 DA02 DA02 DA02 DA02 DA02 DA02 DA02 E7DC F652 0509 139E 21B3 2EF4
Table 9-7 (20). PEQ Parameter Table (f0 = 16.0 [kHz], Q = 0.7)
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CXD2721Q-1
(7) Music Mode Bass Shelving Filter [Relevant coefficients] bLB (address = 76H), gLB (address = 77H), bRB (address = 7AH), gRB (address = 7BH) Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 gLB/gRB 5F65 4531 3061 1FD9 12B7 0849 0000 F96B F431 F00A ECBD EA1F E80A Table 9-8. bLB/bRB fT = 200Hz 7F18 7EDD 7E92 7E33 7DBD 7D29 7C6F 7C6F 7C6F 7C6F 7C6F 7C6F 7C6F fT = 400Hz 7E33 7DBD 7D29 7C6F 7B87 7A65 78FC 78FC 78FC 78FC 78FC 78FC 78FC
(8) Music Mode Treble Shelving Filter [Relevant coefficients] bLT (address = 78H), gLT (address = 79H), bRT (address = 7CH), gRT (address = 7DH) Gain [dB] +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 gLT/gRT 5F65 4531 3061 1FD9 12B7 0849 0000 F96B F431 F00A ECBD EA1F E80A Table 9-9. - 67 - bLT/bRT fT = 200Hz 0EAC 1CF7 2A88 371B 427F 4C9B 556B 556B 556B 556B 556B 556B 556B fT = 400Hz DF91 EDB5 FC51 0B06 1972 2739 3411 3411 3411 3411 3411 3411 3411
CXD2721Q-1
Filter Characteristics ADC Filter Characteristics (43rd + 15th FIR)
Pass band
500.00 400.00 300.00 200.00 0.00 -10.00 -20.00 -30.00
Stop band
Response [dB x 10-3]
100.00 0.00 -100.00 -200.00 -300.00 -400.00 -500.00 -600.00 -700.00 -800.00 0 5 10 Frequency [kHz] 15 20
Response [dB]
-40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 1fs Frequency [kHz] 2fs
DAC Filter Characteristics (43rd + 7th FIR)
Pass band
500.00 400.00 300.00 200.00
Stop band
0.00 -10.00 -20.00 -30.00
Response [dB x 10-3]
100.00
Response [dB]
0.00 -100.00 -200.00 -300.00 -400.00 -500.00 -600.00 -700.00 -800.00 0 5 10 Frequency [kHz] 15 20
-40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 1fs Frequency [kHz] 2fs
- 68 -
Application Circuit
Same as 1 CH1 IN
AGND 20p F 2 31 2 0.01 AGND 330p 2 8 1 CH2 OUT 330k 0.01 AGND AGND 4 AGND AGND AGND AGND AGND 4 10k 3 1000p 330p 10 (2Vrms) 3.3k 10k AOUT2 29 NC 28 NC 27 AVS2 26 LO2 25 AIN2 24 AVD2 23 AVD3 22 D AGND 100p 33k 1 AGND 43 0.01 3 DGND 0.01 AGND AGND 15k 330p AGND AGND LO3 21 AIN3 20 AVS3 19 VDD1 18 VSS2 17 BSL1 16 BSL2 15 DGND 22k DGND 0.01 15k DGND DGND 0.01 DGND XRST DGND DGND 0.01 AGND AGND 3 0.01 AGND AGND 100p 33k 330p 10 1M 1 82 AGND 43 BFOT 14 XWO 13 VSS1 12 VDD1 11 VSS0 10 X768 9 XRST 8 AVS0 7 AVD0 6 NC 5 RVDT 4 NC 3 NC 2 XLAT 1 Microcomputer XTAI CXD2500Q LRCK DA15 DA16 Resistor deviation: 1%; capacitor deviation: 5%. : Digital power supply +5V 5532 operational amplifier used 1 0.01 (2Vrms) CH3 IN 100k AGND 0.01 0.01 0.01 10 82 (2Vrms) CH2 IN 100k AGND 22k AGND C 1 1 12k 10k AGND
AGND
AGND
Same as 2
CH1 OUT
B
E
AGND
AGND
AGND
20p 768fs A
0.01 38 37 0.01 0.01 36 35 34 33 32
0.01
50
49 48
47 46 45
44
43
42 41
40 39
NC
NC
LO1
NC
AIN1
AVS6
XTLI
AVD1
AVS1
AVS4
AVD4
AO1P
XTLO
AVD6
AO1N
AO2P
51 NC AVS5 30
52 NC
0.01
53 VDD2
54 VSS3
DGND DGND
55 TP
56 TP
57 TP
58 TP
59 TP
60 TP
61 TP
62 TP
63 TP
LRCK
TP
XMST
TP
VSS8
VSS6
VDD6
VDD5
SCK
TST0
REDY
TST1
TST2
TST3
VSS7
XS24
SO
SI
BCK
TRDT
- 69 -
94 97 98 95 96 99 100 DGND 0.01 0.01 DGND DGND
64 TP
65 VSS4
AOUT1
DGND
CXD2721Q-1
66 VDD3
0.01
67 TP
DGND
68 TP
69 TP
70 TP
71 TP
72 TP
73 TP
74 TP
75 TP
76 VSS5
DGND
77 VDD4
AO2N
AVD5
NC
0.01
1 : AD operational amplifier +12V power supply 2 : DA operational amplifier +12V power supply 3 : AD operational amplifier -12V power supply 4 : DA operational amplifier -12V power supply
A : Crystal oscillator circuit +5V power supply B : AIN1 +5V power supply C : AIN2 +5V power supply D : AIN3 +5V power supply E : AO1 +5V power supply F : AO2 +5V power supply
78 TP
DGND
79 TP
80 TP
81 82
83
84 85
86 87
88
89 90
91 92 93
DGND
0.01
DGND
CXD2721Q-1
DGND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD2721Q-1
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
- 70 -

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